diff options
Diffstat (limited to 'nuttx')
| -rw-r--r-- | nuttx/Documentation/README.html | 4 | ||||
| -rw-r--r-- | nuttx/README.txt | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h | 30 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h | 1332 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h | 124 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h | 8 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h | 60 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h | 2 | ||||
| -rw-r--r-- | nuttx/arch/arm/src/lpc43xx/lpc43_config.h | 109 | ||||
| -rw-r--r-- | nuttx/configs/README.txt | 4 | ||||
| -rw-r--r-- | nuttx/configs/lpc4330-xplorer/README.txt | 25 | ||||
| -rw-r--r-- | nuttx/configs/lpc4330-xplorer/ostest/defconfig | 64 | ||||
| -rwxr-xr-x | nuttx/configs/stm3210e-eval/include/board.h | 13 | ||||
| -rw-r--r-- | nuttx/configs/stm3210e-eval/src/stm3210e-internal.h | 13 |
16 files changed, 962 insertions, 844 deletions
diff --git a/nuttx/Documentation/README.html b/nuttx/Documentation/README.html index 3037927789..7f84acddf6 100644 --- a/nuttx/Documentation/README.html +++ b/nuttx/Documentation/README.html @@ -8,7 +8,7 @@ <tr align="center" bgcolor="#e4e4e4"> <td> <h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1> - <p>Last Updated: June 29, 2012</p> + <p>Last Updated: July 4, 2012</p> </td> </tr> </table> @@ -107,6 +107,8 @@ | | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/lm3s8962-ek/README.txt?view=log"><b><i>README.txt</i></b></a> | | |- lpcxpresso-lpc1768/ | | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/lpcxpresso-lpc1768/README.txt?view=log"><b><i>README.txt</i></b></a> + | | |- lpc4330-xplorer/ + | | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/llpc4330-xplorer/README.txt?view=log"><b><i>README.txt</i></b></a> | | |- m68332evb/ | | | |- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/m68332evb/include/README.txt?view=log">include/README.txt</a> | | | `- <a href="http://nuttx.svn.sourceforge.net/viewvc/nuttx/trunk/nuttx/configs/m68332evb/src/README.txt?view=log">src/README.txt</a> diff --git a/nuttx/README.txt b/nuttx/README.txt index 84af2b8e7f..66f3aa3ec0 100644 --- a/nuttx/README.txt +++ b/nuttx/README.txt @@ -670,6 +670,8 @@ nuttx | | `- README.txt | |- lpcxpresso-lpc1768/ | | `- README.txt + | |- lpc4330-xplorer/ + | | `- README.txt | |- m68332evb/ | | |- include/README.txt | | `- src/README.txt diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h index 03d26c9037..ff7b4c9ab7 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_ccu.h @@ -111,8 +111,8 @@ #define LPC43_CCU1_M4_EEPROM_STAT_OFFSET 0x04a4 /* CLK_M4_EEPROM status register */ #define LPC43_CCU1_M4_WWDT_CFG_OFFSET 0x0500 /* CLK_M4_WWDT configuration register */ #define LPC43_CCU1_M4_WWDT_STAT_OFFSET 0x0504 /* CLK_M4_WWDT status register */ -#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_UART0 configuration register */ -#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_UART0 status register */ +#define LPC43_CCU1_M4_USART0_CFG_OFFSET 0x0508 /* CLK_M4_USART0 configuration register */ +#define LPC43_CCU1_M4_USART0_STAT_OFFSET 0x050c /* CLK_M4_USART0 status register */ #define LPC43_CCU1_M4_UART1_CFG_OFFSET 0x0510 /* CLK_M4_UART1 configuration register */ #define LPC43_CCU1_M4_UART1_STAT_OFFSET 0x0514 /* CLK_M4_UART1 status register */ #define LPC43_CCU1_M4_SSP0_CFG_OFFSET 0x0518 /* CLK_M4_SSP0 configuration register */ @@ -127,10 +127,10 @@ #define LPC43_CCU1_M4_CREG_STAT_OFFSET 0x053c /* CLK_M4_CREG status register */ #define LPC43_CCU1_M4_RITIMER_CFG_OFFSET 0x0600 /* CLK_M4_RITIMER configuration register */ #define LPC43_CCU1_M4_RITIMER_STAT_OFFSET 0x0604 /* CLK_M4_RITIMER status register */ -#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_UART2 configuration register */ -#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_UART2 status register */ -#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_UART3 configuration register */ -#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_UART3 status register */ +#define LPC43_CCU1_M4_USART2_CFG_OFFSET 0x0608 /* CLK_M4_USART2 configuration register */ +#define LPC43_CCU1_M4_USART2_STAT_OFFSET 0x060c /* CLK_M4_USART2 status register */ +#define LPC43_CCU1_M4_USART3_CFG_OFFSET 0x0610 /* CLK_M4_USART3 configuration register */ +#define LPC43_CCU1_M4_USART3_STAT_OFFSET 0x0614 /* CLK_M4_USART3 status register */ #define LPC43_CCU1_M4_TIMER2_CFG_OFFSET 0x0618 /* CLK_M4_TIMER2 configuration register */ #define LPC43_CCU1_M4_TIMER2_STAT_OFFSET 0x061c /* CLK_M4_TIMER2 status register */ #define LPC43_CCU1_M4_TIMER3_CFG_OFFSET 0x0620 /* CLK_M4_TIMER3 configuration register */ @@ -158,14 +158,14 @@ #define LPC43_CCU2_BASE_STAT_OFFSET 0x0004 /* CCU2 base clocks status register */ #define LPC43_CCU2_APLL_CFG_OFFSET 0x0100 /* CLK_APLL configuration register */ #define LPC43_CCU2_APLL_STAT_OFFSET 0x0104 /* CLK_APLL status register */ -#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_UART3 configuration register */ -#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_UART3 status register */ -#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_UART2 configuration register */ -#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_UART2 status register */ +#define LPC43_CCU2_APB2_USART3_CFG_OFFSET 0x0200 /* CLK_APB2_USART3 configuration register */ +#define LPC43_CCU2_APB2_USART3_STAT_OFFSET 0x0204 /* CLK_APB2_USART3 status register */ +#define LPC43_CCU2_APB2_USART2_CFG_OFFSET 0x0300 /* CLK_APB2_USART2 configuration register */ +#define LPC43_CCU2_APB2_USART2_STAT_OFFSET 0x0304 /* CLK_APB2_USART2 status register */ #define LPC43_CCU2_APB0_UART1_CFG_OFFSET 0x0400 /* CLK_APB0_UART1 configuration register */ #define LPC43_CCU2_APB0_UART1_STAT_OFFSET 0x0404 /* CLK_APB0_UART1 status register */ -#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_UART0 configuration register */ -#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_UART0 status register */ +#define LPC43_CCU2_APB0_USART0_CFG_OFFSET 0x0500 /* CLK_APB0_USART0 configuration register */ +#define LPC43_CCU2_APB0_USART0_STAT_OFFSET 0x0504 /* CLK_APB0_USART0 status register */ #define LPC43_CCU2_APB2_SSP1_CFG_OFFSET 0x0600 /* CLK_APB2_SSP1 configuration register */ #define LPC43_CCU2_APB2_SSP1_STAT_OFFSET 0x0604 /* CLK_APB2_SSP1 status register */ #define LPC43_CCU2_APB0_SSP0_CFG_OFFSET 0x0700 /* CLK_APB0_SSP0 configuration register */ @@ -321,10 +321,10 @@ /* Bits 10-31: Reserved */ /* CCU2 Base Clock Status Register */ /* Bit 0: Reserved */ -#define CCU2_BASE_STAT_UART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_UART3_CLK */ -#define CCU2_BASE_STAT_UART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_UART2_CLK */ +#define CCU2_BASE_STAT_USART3 (1 << 1) /* Bit 1: Base clock indicator for BASE_USART3_CLK */ +#define CCU2_BASE_STAT_USART2 (1 << 2) /* Bit 2: Base clock indicator for BASE_USART2_CLK */ #define CCU2_BASE_STAT_UART1 (1 << 3) /* Bit 3: Base clock indicator for BASE_UART1_CLK */ -#define CCU2_BASE_STAT_UART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_UART0_CLK */ +#define CCU2_BASE_STAT_USART0 (1 << 4) /* Bit 4: Base clock indicator for BASE_USART0_CLK */ #define CCU2_BASE_STAT_SSP1 (1 << 5) /* Bit 5: Base clock indicator for BASE_SSP1_CLK */ #define CCU2_BASE_STAT_SSP0 (1 << 6) /* Bit 6: Base clock indicator for BASE_SSP0_CLK */ /* Bits 7-31: Reserved */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h index 255d88b420..c07f521d22 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_cgu.h @@ -47,380 +47,380 @@ ****************************************************************************************************/ /* Register Offsets *********************************************************************************/ -#define LPC43_FREQ_MON_OFFSET 0x014 /* Frequency monitor register */ -#define LPC43_XTAL_OSC_CTRL_OFFSET 0x018 /* Crystal oscillator control register */ -#define LPC43_PLL0USB_STAT_OFFSET 0x01c /* PLL0USB status register */ -#define LPC43_PLL0USB_CTRL_OFFSET 0x020 /* PLL0USB control register */ -#define LPC43_PLL0USB_MDIV_OFFSET 0x024 /* PLL0USB M-divider register */ -#define LPC43_PLL0USB_NP_DIV_OFFSET 0x028 /* PLL0USB N/P-divider register */ -#define LPC43_PLL0AUDIO_STAT_OFFSET 0x02c /* PLL0AUDIO status register */ -#define LPC43_PLL0AUDIO_CTRL_OFFSET 0x030 /* PLL0AUDIO control register */ -#define LPC43_PLL0AUDIO_MDIV_OFFSET 0x034 /* PLL0AUDIO M-divider */ -#define LPC43_PLL0AUDIO_NP_DIV_OFFSET 0x038 /* PLL0AUDIO N/P-divider */ -#define LPC43_PLL0AUDIO_FRAC_OFFSET 0x03c /* PLL0AUDIO fractional */ -#define LPC43_PLL1_STAT_OFFSET 0x040 /* PLL1 status register */ -#define LPC43_PLL1_CTRL_OFFSET 0x044 /* PLL1 control register */ -#define LPC43_IDIVA_CTRL_OFFSET 0x048 /* Integer divider A control register */ -#define LPC43_IDIVB_CTRL_OFFSET 0x04c /* Integer divider B control register */ -#define LPC43_IDIVC_CTRL_OFFSET 0x050 /* Integer divider C control register */ -#define LPC43_IDIVD_CTRL_OFFSET 0x054 /* Integer divider D control register */ -#define LPC43_IDIVE_CTRL_OFFSET 0x058 /* Integer divider E control register */ -#define LPC43_BASE_SAFE_CLK_OFFSET 0x05c /* Output stage 0 control register (BASE_SAFE_CLK) */ -#define LPC43_BASE_USB0_CLK_OFFSET 0x060 /* Output stage 1 control register (BASE_USB0_CLK) */ -#define LPC43_BASE_PERIPH_CLK_OFFSET 0x064 /* Output stage 2 control register (BASE_PERIPH_CLK) */ -#define LPC43_BASE_USB1_CLK_OFFSET 0x068 /* Output stage 3 control register (BASE_USB1_CLK) */ -#define LPC43_BASE_M4_CLK_OFFSET 0x06c /* Output stage 4 control register (BASE_M4_CLK) */ -#define LPC43_BASE_SPIFI_CLK_OFFSET 0x070 /* Output stage 5 control register (BASE_SPIFI_CLK) */ -#define LPC43_BASE_SPI_CLK_OFFSET 0x074 /* Output stage 6 control register (BASE_SPI_CLK) */ -#define LPC43_BASE_PHYRX_CLK_OFFSET 0x078 /* Output stage 7 control register (BASE_PHY_RX_CLK) */ -#define LPC43_BASE_PHYTX_CLK_OFFSET 0x07c /* Output stage 8 control register (BASE_PHY_TX_CLK) */ -#define LPC43_BASE_APB1_CLK_OFFSET 0x080 /* Output stage 9 control register (BASE_APB1_CLK) */ -#define LPC43_BASE_APB3_CLK_OFFSET 0x084 /* Output stage 10 control register (BASE_APB3_CLK) */ -#define LPC43_BASE_LCD_CLK_OFFSET 0x088 /* Output stage 11 control register (BASE_LCD_CLK) */ -#define LPC43_BASE_VADC_CLK_OFFSET 0x08c /* Output stage 12 control register (BASE_VADC_CLK) */ -#define LPC43_BASE_SDIO_CLK_OFFSET 0x090 /* Output stage 13 control register (BASE_SDIO_CLK) */ -#define LPC43_BASE_SSP0_CLK_OFFSET 0x094 /* Output stage 14 control register (BASE_SSP0_CLK) */ -#define LPC43_BASE_SSP1_CLK_OFFSET 0x098 /* Output stage 15 control register (BASE_SSP1_CLK) */ -#define LPC43_BASE_UART0_CLK_OFFSET 0x09c /* Output stage 16 control register (BASE_UART0_CLK) */ -#define LPC43_BASE_UART1_CLK_OFFSET 0x0a0 /* Output stage 17 control register (BASE_UART1_CLK) */ -#define LPC43_BASE_UART2_CLK_OFFSET 0x0a4 /* Output stage 18 control register (BASE_UART2_CLK) */ -#define LPC43_BASE_UART3_CLK_OFFSET 0x0a8 /* Output stage 19 control register (BASE_UART3_CLK) */ -#define LPC43_BASE_OUT_CLK_OFFSET 0x0ac /* Output stage 20 control register (BASE_OUT_CLK) */ -#define LPC43_BASE_APLL_CLK_OFFSET 0x0c0 /* Output stage 25 control register (BASE_APLL_CLK) */ -#define LPC43_BASE_CGU_OUT0_CLK_OFFSET 0x0c4 /* Output stage 26 control register (BASE_CGU_OUT0_CLK) */ -#define LPC43_BASE_CGU_OUT1_CLK_OFFSET 0x0c8 /* Output stage 27 control register (BASE_CGU_OUT1_CLK) */ +#define LPC43_FREQ_MON_OFFSET 0x0014 /* Frequency monitor register */ +#define LPC43_XTAL_OSC_CTRL_OFFSET 0x0018 /* Crystal oscillator control register */ +#define LPC43_PLL0USB_STAT_OFFSET 0x001c /* PLL0USB status register */ +#define LPC43_PLL0USB_CTRL_OFFSET 0x0020 /* PLL0USB control register */ +#define LPC43_PLL0USB_MDIV_OFFSET 0x0024 /* PLL0USB M-divider register */ +#define LPC43_PLL0USB_NP_DIV_OFFSET 0x0028 /* PLL0USB N/P-divider register */ +#define LPC43_PLL0AUDIO_STAT_OFFSET 0x002c /* PLL0AUDIO status register */ +#define LPC43_PLL0AUDIO_CTRL_OFFSET 0x0030 /* PLL0AUDIO control register */ +#define LPC43_PLL0AUDIO_MDIV_OFFSET 0x0034 /* PLL0AUDIO M-divider */ +#define LPC43_PLL0AUDIO_NP_DIV_OFFSET 0x0038 /* PLL0AUDIO N/P-divider */ +#define LPC43_PLL0AUDIO_FRAC_OFFSET 0x003c /* PLL0AUDIO fractional */ +#define LPC43_PLL1_STAT_OFFSET 0x0040 /* PLL1 status register */ +#define LPC43_PLL1_CTRL_OFFSET 0x0044 /* PLL1 control register */ +#define LPC43_IDIVA_CTRL_OFFSET 0x0048 /* Integer divider A control register */ +#define LPC43_IDIVB_CTRL_OFFSET 0x004c /* Integer divider B control register */ +#define LPC43_IDIVC_CTRL_OFFSET 0x0050 /* Integer divider C control register */ +#define LPC43_IDIVD_CTRL_OFFSET 0x0054 /* Integer divider D control register */ +#define LPC43_IDIVE_CTRL_OFFSET 0x0058 /* Integer divider E control register */ +#define LPC43_BASE_SAFE_CLK_OFFSET 0x005c /* Output stage 0 control register (BASE_SAFE_CLK) */ +#define LPC43_BASE_USB0_CLK_OFFSET 0x0060 /* Output stage 1 control register (BASE_USB0_CLK) */ +#define LPC43_BASE_PERIPH_CLK_OFFSET 0x0064 /* Output stage 2 control register (BASE_PERIPH_CLK) */ +#define LPC43_BASE_USB1_CLK_OFFSET 0x0068 /* Output stage 3 control register (BASE_USB1_CLK) */ +#define LPC43_BASE_M4_CLK_OFFSET 0x006c /* Output stage 4 control register (BASE_M4_CLK) */ +#define LPC43_BASE_SPIFI_CLK_OFFSET 0x0070 /* Output stage 5 control register (BASE_SPIFI_CLK) */ +#define LPC43_BASE_SPI_CLK_OFFSET 0x0074 /* Output stage 6 control register (BASE_SPI_CLK) */ +#define LPC43_BASE_PHYRX_CLK_OFFSET 0x0078 /* Output stage 7 control register (BASE_PHY_RX_CLK) */ +#define LPC43_BASE_PHYTX_CLK_OFFSET 0x007c /* Output stage 8 control register (BASE_PHY_TX_CLK) */ +#define LPC43_BASE_APB1_CLK_OFFSET 0x0080 /* Output stage 9 control register (BASE_APB1_CLK) */ +#define LPC43_BASE_APB3_CLK_OFFSET 0x0084 /* Output stage 10 control register (BASE_APB3_CLK) */ +#define LPC43_BASE_LCD_CLK_OFFSET 0x0088 /* Output stage 11 control register (BASE_LCD_CLK) */ +#define LPC43_BASE_VADC_CLK_OFFSET 0x008c /* Output stage 12 control register (BASE_VADC_CLK) */ +#define LPC43_BASE_SDIO_CLK_OFFSET 0x0090 /* Output stage 13 control register (BASE_SDIO_CLK) */ +#define LPC43_BASE_SSP0_CLK_OFFSET 0x0094 /* Output stage 14 control register (BASE_SSP0_CLK) */ +#define LPC43_BASE_SSP1_CLK_OFFSET 0x0098 /* Output stage 15 control register (BASE_SSP1_CLK) */ +#define LPC43_BASE_USART0_CLK_OFFSET 0x009c /* Output stage 16 control register (BASE_USART0_CLK) */ +#define LPC43_BASE_UART1_CLK_OFFSET 0x00a0 /* Output stage 17 control register (BASE_UART1_CLK) */ +#define LPC43_BASE_USART2_CLK_OFFSET 0x00a4 /* Output stage 18 control register (BASE_USART2_CLK) */ +#define LPC43_BASE_USART3_CLK_OFFSET 0x00a8 /* Output stage 19 control register (BASE_USART3_CLK) */ +#define LPC43_BASE_OUT_CLK_OFFSET 0x00ac /* Output stage 20 control register (BASE_OUT_CLK) */ +#define LPC43_BASE_APLL_CLK_OFFSET 0x00c0 /* Output stage 25 control register (BASE_APLL_CLK) */ +#define LPC43_BASE_CGU_OUT0_CLK_OFFSET 0x00c4 /* Output stage 26 control register (BASE_CGU_OUT0_CLK) */ +#define LPC43_BASE_CGU_OUT1_CLK_OFFSET 0x00c8 /* Output stage 27 control register (BASE_CGU_OUT1_CLK) */ /* Register Addresses *******************************************************************************/ -#define LPC43_FREQ_MON (LPC43_CGU_BASE+LPC43_FREQ_MON_OFFSET) -#define LPC43_XTAL_OSC_CTRL (LPC43_CGU_BASE+LPC43_XTAL_OSC_CTRL_OFFSET) -#define LPC43_PLL0USB_STAT (LPC43_CGU_BASE+LPC43_PLL0USB_STAT_OFFSET) -#define LPC43_PLL0USB_CTRL (LPC43_CGU_BASE+LPC43_PLL0USB_CTRL_OFFSET) -#define LPC43_PLL0USB_MDIV (LPC43_CGU_BASE+LPC43_PLL0USB_MDIV_OFFSET) -#define LPC43_PLL0USB_NP_DIV (LPC43_CGU_BASE+LPC43_PLL0USB_NP_DIV_OFFSET) -#define LPC43_PLL0AUDIO_STAT (LPC43_CGU_BASE+LPC43_PLL0AUDIO_STAT_OFFSET) -#define LPC43_PLL0AUDIO_CTRL (LPC43_CGU_BASE+LPC43_PLL0AUDIO_CTRL_OFFSET) -#define LPC43_PLL0AUDIO_MDIV (LPC43_CGU_BASE+LPC43_PLL0AUDIO_MDIV_OFFSET) -#define LPC43_PLL0AUDIO_NP_DIV (LPC43_CGU_BASE+LPC43_PLL0AUDIO_NP_DIV_OFFSET) -#define LPC43_PLL0AUDIO_FRAC (LPC43_CGU_BASE+LPC43_PLL0AUDIO_FRAC_OFFSET) -#define LPC43_PLL1_STAT (LPC43_CGU_BASE+LPC43_PLL1_STAT_OFFSET) -#define LPC43_PLL1_CTRL (LPC43_CGU_BASE+LPC43_PLL1_CTRL_OFFSET) -#define LPC43_IDIVA_CTRL (LPC43_CGU_BASE+LPC43_IDIVA_CTRL_OFFSET) -#define LPC43_IDIVB_CTRL (LPC43_CGU_BASE+LPC43_IDIVB_CTRL_OFFSET) -#define LPC43_IDIVC_CTRL (LPC43_CGU_BASE+LPC43_IDIVC_CTRL_OFFSET) -#define LPC43_IDIVD_CTRL (LPC43_CGU_BASE+LPC43_IDIVD_CTRL_OFFSET) -#define LPC43_IDIVE_CTRL (LPC43_CGU_BASE+LPC43_IDIVE_CTRL_OFFSET) -#define LPC43_BASE_SAFE_CLK (LPC43_CGU_BASE+LPC43_BASE_SAFE_CLK_OFFSET) -#define LPC43_BASE_USB0_CLK (LPC43_CGU_BASE+LPC43_BASE_USB0_CLK_OFFSET) -#define LPC43_BASE_PERIPH_CLK (LPC43_CGU_BASE+LPC43_BASE_PERIPH_CLK_OFFSET) -#define LPC43_BASE_USB1_CLK (LPC43_CGU_BASE+LPC43_BASE_USB1_CLK_OFFSET) -#define LPC43_BASE_M4_CLK (LPC43_CGU_BASE+LPC43_BASE_M4_CLK_OFFSET) -#define LPC43_BASE_SPIFI_CLK (LPC43_CGU_BASE+LPC43_BASE_SPIFI_CLK_OFFSET) -#define LPC43_BASE_SPI_CLK (LPC43_CGU_BASE+LPC43_BASE_SPI_CLK_OFFSET) -#define LPC43_BASE_PHYRX_CLK (LPC43_CGU_BASE+LPC43_BASE_PHYRX_CLK_OFFSET) -#define LPC43_BASE_PHYTX_CLK (LPC43_CGU_BASE+LPC43_BASE_PHYTX_CLK_OFFSET) -#define LPC43_BASE_APB1_CLK (LPC43_CGU_BASE+LPC43_BASE_APB1_CLK_OFFSET) -#define LPC43_BASE_APB3_CLK (LPC43_CGU_BASE+LPC43_BASE_APB3_CLK_OFFSET) -#define LPC43_BASE_LCD_CLK (LPC43_CGU_BASE+LPC43_BASE_LCD_CLK_OFFSET) -#define LPC43_BASE_VADC_CLK (LPC43_CGU_BASE+LPC43_BASE_VADC_CLK_OFFSET) -#define LPC43_BASE_SDIO_CLK (LPC43_CGU_BASE+LPC43_BASE_SDIO_CLK_OFFSET) -#define LPC43_BASE_SSP0_CLK (LPC43_CGU_BASE+LPC43_BASE_SSP0_CLK_OFFSET) -#define LPC43_BASE_SSP1_CLK (LPC43_CGU_BASE+LPC43_BASE_SSP1_CLK_OFFSET) -#define LPC43_BASE_UART0_CLK (LPC43_CGU_BASE+LPC43_BASE_UART0_CLK_OFFSET) -#define LPC43_BASE_UART1_CLK (LPC43_CGU_BASE+LPC43_BASE_UART1_CLK_OFFSET) -#define LPC43_BASE_UART2_CLK (LPC43_CGU_BASE+LPC43_BASE_UART2_CLK_OFFSET) -#define LPC43_BASE_UART3_CLK (LPC43_CGU_BASE+LPC43_BASE_UART3_CLK_OFFSET) -#define LPC43_BASE_OUT_CLK (LPC43_CGU_BASE+LPC43_BASE_OUT_CLK_OFFSET) -#define LPC43_BASE_APLL_CLK (LPC43_CGU_BASE+LPC43_BASE_APLL_CLK_OFFSET) -#define LPC43_BASE_CGU_OUT0_CLK (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT0_CLK_OFFSET) -#define LPC43_BASE_CGU_OUT1_CLK (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT1_CLK_OFFSET) +#define LPC43_FREQ_MON (LPC43_CGU_BASE+LPC43_FREQ_MON_OFFSET) +#define LPC43_XTAL_OSC_CTRL (LPC43_CGU_BASE+LPC43_XTAL_OSC_CTRL_OFFSET) +#define LPC43_PLL0USB_STAT (LPC43_CGU_BASE+LPC43_PLL0USB_STAT_OFFSET) +#define LPC43_PLL0USB_CTRL (LPC43_CGU_BASE+LPC43_PLL0USB_CTRL_OFFSET) +#define LPC43_PLL0USB_MDIV (LPC43_CGU_BASE+LPC43_PLL0USB_MDIV_OFFSET) +#define LPC43_PLL0USB_NP_DIV (LPC43_CGU_BASE+LPC43_PLL0USB_NP_DIV_OFFSET) +#define LPC43_PLL0AUDIO_STAT (LPC43_CGU_BASE+LPC43_PLL0AUDIO_STAT_OFFSET) +#define LPC43_PLL0AUDIO_CTRL (LPC43_CGU_BASE+LPC43_PLL0AUDIO_CTRL_OFFSET) +#define LPC43_PLL0AUDIO_MDIV (LPC43_CGU_BASE+LPC43_PLL0AUDIO_MDIV_OFFSET) +#define LPC43_PLL0AUDIO_NP_DIV (LPC43_CGU_BASE+LPC43_PLL0AUDIO_NP_DIV_OFFSET) +#define LPC43_PLL0AUDIO_FRAC (LPC43_CGU_BASE+LPC43_PLL0AUDIO_FRAC_OFFSET) +#define LPC43_PLL1_STAT (LPC43_CGU_BASE+LPC43_PLL1_STAT_OFFSET) +#define LPC43_PLL1_CTRL (LPC43_CGU_BASE+LPC43_PLL1_CTRL_OFFSET) +#define LPC43_IDIVA_CTRL (LPC43_CGU_BASE+LPC43_IDIVA_CTRL_OFFSET) +#define LPC43_IDIVB_CTRL (LPC43_CGU_BASE+LPC43_IDIVB_CTRL_OFFSET) +#define LPC43_IDIVC_CTRL (LPC43_CGU_BASE+LPC43_IDIVC_CTRL_OFFSET) +#define LPC43_IDIVD_CTRL (LPC43_CGU_BASE+LPC43_IDIVD_CTRL_OFFSET) +#define LPC43_IDIVE_CTRL (LPC43_CGU_BASE+LPC43_IDIVE_CTRL_OFFSET) +#define LPC43_BASE_SAFE_CLK (LPC43_CGU_BASE+LPC43_BASE_SAFE_CLK_OFFSET) +#define LPC43_BASE_USB0_CLK (LPC43_CGU_BASE+LPC43_BASE_USB0_CLK_OFFSET) +#define LPC43_BASE_PERIPH_CLK (LPC43_CGU_BASE+LPC43_BASE_PERIPH_CLK_OFFSET) +#define LPC43_BASE_USB1_CLK (LPC43_CGU_BASE+LPC43_BASE_USB1_CLK_OFFSET) +#define LPC43_BASE_M4_CLK (LPC43_CGU_BASE+LPC43_BASE_M4_CLK_OFFSET) +#define LPC43_BASE_SPIFI_CLK (LPC43_CGU_BASE+LPC43_BASE_SPIFI_CLK_OFFSET) +#define LPC43_BASE_SPI_CLK (LPC43_CGU_BASE+LPC43_BASE_SPI_CLK_OFFSET) +#define LPC43_BASE_PHYRX_CLK (LPC43_CGU_BASE+LPC43_BASE_PHYRX_CLK_OFFSET) +#define LPC43_BASE_PHYTX_CLK (LPC43_CGU_BASE+LPC43_BASE_PHYTX_CLK_OFFSET) +#define LPC43_BASE_APB1_CLK (LPC43_CGU_BASE+LPC43_BASE_APB1_CLK_OFFSET) +#define LPC43_BASE_APB3_CLK (LPC43_CGU_BASE+LPC43_BASE_APB3_CLK_OFFSET) +#define LPC43_BASE_LCD_CLK (LPC43_CGU_BASE+LPC43_BASE_LCD_CLK_OFFSET) +#define LPC43_BASE_VADC_CLK (LPC43_CGU_BASE+LPC43_BASE_VADC_CLK_OFFSET) +#define LPC43_BASE_SDIO_CLK (LPC43_CGU_BASE+LPC43_BASE_SDIO_CLK_OFFSET) +#define LPC43_BASE_SSP0_CLK (LPC43_CGU_BASE+LPC43_BASE_SSP0_CLK_OFFSET) +#define LPC43_BASE_SSP1_CLK (LPC43_CGU_BASE+LPC43_BASE_SSP1_CLK_OFFSET) +#define LPC43_BASE_USART0_CLK (LPC43_CGU_BASE+LPC43_BASE_USART0_CLK_OFFSET) +#define LPC43_BASE_UART1_CLK (LPC43_CGU_BASE+LPC43_BASE_UART1_CLK_OFFSET) +#define LPC43_BASE_USART2_CLK (LPC43_CGU_BASE+LPC43_BASE_USART2_CLK_OFFSET) +#define LPC43_BASE_USART3_CLK (LPC43_CGU_BASE+LPC43_BASE_USART3_CLK_OFFSET) +#define LPC43_BASE_OUT_CLK (LPC43_CGU_BASE+LPC43_BASE_OUT_CLK_OFFSET) +#define LPC43_BASE_APLL_CLK (LPC43_CGU_BASE+LPC43_BASE_APLL_CLK_OFFSET) +#define LPC43_BASE_CGU_OUT0_CLK (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT0_CLK_OFFSET) +#define LPC43_BASE_CGU_OUT1_CLK (LPC43_CGU_BASE+LPC43_BASE_CGU_OUT1_CLK_OFFSET) /* Register Bit Definitions *************************************************************************/ /* Frequency monitor register */ -#define FREQ_MON_RCNT_SHIFT (0) /* Bits 0-8: 9-bit reference clock-counter value */ -#define FREQ_MON_RCNT_MASK (0x1ff << FREQ_MON_RCNT_SHIFT) -#define FREQ_MON_FCNT_SHIFT (9) /* Bits 9-22: 14-bit selected clock-counter value */ -#define FREQ_MON_FCNT_MASK (0x3fff << FREQ_MON_FCNT_SHIFT) -#define FREQ_MON_MEAS (1 << 23) /* Bit 23: Measure frequency */ -#define FREQ_MON_CLKSEL_SHIFT (24) /* Bits 24-28: Clock-source selection */ -#define FREQ_MON_CLKSEL_MASK (31 << FREQ_MON_CLKSEL_SHIFT) -# define FREQ_MON_CLKSEL_32KHZOSC (0 << FREQ_MON_CLKSEL_SHIFT) /* 32 kHz oscillator (default) */ -# define FREQ_MON_CLKSEL_IRQ (1 << FREQ_MON_CLKSEL_SHIFT) /* IRC */ -# define FREQ_MON_CLKSEL_ENET_RXCLK (2 << FREQ_MON_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define FREQ_MON_CLKSEL_ENET_TXCLK (3 << FREQ_MON_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define FREQ_MON_CLKSEL_GPCLKIN (4 << FREQ_MON_CLKSEL_SHIFT) /* GP_CLKIN */ -# define FREQ_MON_CLKSEL_XTAL (6 << FREQ_MON_CLKSEL_SHIFT) /* Crystal oscillator */ -# define FREQ_MON_CLKSEL_PLL0USB (7 << FREQ_MON_CLKSEL_SHIFT) /* PLL0USB */ -# define FREQ_MON_CLKSEL_PLL0AUDIO (8 << FREQ_MON_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define FREQ_MON_CLKSEL_PLL1 (9 << FREQ_MON_CLKSEL_SHIFT) /* PLL1 */ -# define FREQ_MON_CLKSEL_IDIVA (12 << FREQ_MON_CLKSEL_SHIFT) /* IDIVA */ -# define FREQ_MON_CLKSEL_IDIVB (13 << FREQ_MON_CLKSEL_SHIFT) /* IDIVB */ -# define FREQ_MON_CLKSEL_IDIVC (14 << FREQ_MON_CLKSEL_SHIFT) /* IDIVC */ -# define FREQ_MON_CLKSEL_IDIVD (15 << FREQ_MON_CLKSEL_SHIFT) /* IDIVD */ -# define FREQ_MON_CLKSEL_IDIVE (16 << FREQ_MON_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define FREQ_MON_RCNT_SHIFT (0) /* Bits 0-8: 9-bit reference clock-counter value */ +#define FREQ_MON_RCNT_MASK (0x1ff << FREQ_MON_RCNT_SHIFT) +#define FREQ_MON_FCNT_SHIFT (9) /* Bits 9-22: 14-bit selected clock-counter value */ +#define FREQ_MON_FCNT_MASK (0x3fff << FREQ_MON_FCNT_SHIFT) +#define FREQ_MON_MEAS (1 << 23) /* Bit 23: Measure frequency */ +#define FREQ_MON_CLKSEL_SHIFT (24) /* Bits 24-28: Clock-source selection */ +#define FREQ_MON_CLKSEL_MASK (31 << FREQ_MON_CLKSEL_SHIFT) +# define FREQ_MON_CLKSEL_32KHZOSC (0 << FREQ_MON_CLKSEL_SHIFT) /* 32 kHz oscillator (default) */ +# define FREQ_MON_CLKSEL_IRQ (1 << FREQ_MON_CLKSEL_SHIFT) /* IRC */ +# define FREQ_MON_CLKSEL_ENET_RXCLK (2 << FREQ_MON_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define FREQ_MON_CLKSEL_ENET_TXCLK (3 << FREQ_MON_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define FREQ_MON_CLKSEL_GPCLKIN (4 << FREQ_MON_CLKSEL_SHIFT) /* GP_CLKIN */ +# define FREQ_MON_CLKSEL_XTAL (6 << FREQ_MON_CLKSEL_SHIFT) /* Crystal oscillator */ +# define FREQ_MON_CLKSEL_PLL0USB (7 << FREQ_MON_CLKSEL_SHIFT) /* PLL0USB */ +# define FREQ_MON_CLKSEL_PLL0AUDIO (8 << FREQ_MON_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define FREQ_MON_CLKSEL_PLL1 (9 << FREQ_MON_CLKSEL_SHIFT) /* PLL1 */ +# define FREQ_MON_CLKSEL_IDIVA (12 << FREQ_MON_CLKSEL_SHIFT) /* IDIVA */ +# define FREQ_MON_CLKSEL_IDIVB (13 << FREQ_MON_CLKSEL_SHIFT) /* IDIVB */ +# define FREQ_MON_CLKSEL_IDIVC (14 << FREQ_MON_CLKSEL_SHIFT) /* IDIVC */ +# define FREQ_MON_CLKSEL_IDIVD (15 << FREQ_MON_CLKSEL_SHIFT) /* IDIVD */ +# define FREQ_MON_CLKSEL_IDIVE (16 << FREQ_MON_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Crystal oscillator control register */ -#define XTAL_OSC_CTRL_ENABLE (1 << 0) /* Bit 0: Oscillator-pad enable */ -#define XTAL_OSC_CTRL_BYPASS (1 << 1) /* Bit 1: Configure crystal or external-clock input */ -#define XTAL_OSC_CTRL_HF (1 << 2) /* Bit 2: Select frequency range - /* Bits 3-31: Reserved */ +#define XTAL_OSC_CTRL_ENABLE (1 << 0) /* Bit 0: Oscillator-pad enable */ +#define XTAL_OSC_CTRL_BYPASS (1 << 1) /* Bit 1: Configure crystal or external-clock input */ +#define XTAL_OSC_CTRL_HF (1 << 2) /* Bit 2: Select frequency range + /* Bits 3-31: Reserved */ /* PLL0USB status register */ -#define PLL0USB_STAT_LOCK (1 << 0) /* Bit 0: PLL0 lock indicator */ -#define PLL0USB_STAT_FR (1 << 1) /* Bit 1: PLL0 free running indicator */ - /* Bits 2-31: Reserved */ +#define PLL0USB_STAT_LOCK (1 << 0) /* Bit 0: PLL0 lock indicator */ +#define PLL0USB_STAT_FR (1 << 1) /* Bit 1: PLL0 free running indicator */ + /* Bits 2-31: Reserved */ /* PLL0USB control register */ -#define PLL0USB_CTRL_PD (1 << 0) /* Bit 0: PLL0 power down */ -#define PLL0USB_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */ -#define PLL0USB_CTRL_DIRECTI (1 << 2) /* Bit 2: PLL0 direct input */ -#define PLL0USB_CTRL_DIRECTO (1 << 3) /* Bit 3: PLL0 direct output */ -#define PLL0USB_CTRL_CLKEN (1 << 4) /* Bit 4: PLL0 clock enable */ - /* Bit 5: Reserved */ -#define PLL0USB_CTRL_FRM (1 << 6) /* Bit 6: Free running mode */ - /* Bits 7-10: Reserved */ -#define PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define PLL0USB_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define PLL0USB_CTRL_CLKSEL_MASK (31 << PLL0USB_CTRL_CLKSEL_SHIFT) -# define PLL0USB_CLKSEL_32KHZOSC (0 << PLL0USB_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define PLL0USB_CLKSEL_IRC (1 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define PLL0USB_CLKSEL_ENET_RXCLK (2 << PLL0USB_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define PLL0USB_CLKSEL_ENET_TXCLK (3 << PLL0USB_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define PLL0USB_CLKSEL_GPCLKIN (4 << PLL0USB_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define PLL0USB_CLKSEL_XTAL (6 << PLL0USB_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define PLL0USB_CLKSEL_PLL1 (9 << PLL0USB_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define PLL0USB_CLKSEL_IDIVA (12 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define PLL0USB_CLKSEL_IDIVB (13 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define PLL0USB_CLKSEL_IDIVC (14 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define PLL0USB_CLKSEL_IDIVD (15 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define PLL0USB_CLKSEL_IDIVE (16 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define PLL0USB_CTRL_PD (1 << 0) /* Bit 0: PLL0 power down */ +#define PLL0USB_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */ +#define PLL0USB_CTRL_DIRECTI (1 << 2) /* Bit 2: PLL0 direct input */ +#define PLL0USB_CTRL_DIRECTO (1 << 3) /* Bit 3: PLL0 direct output */ +#define PLL0USB_CTRL_CLKEN (1 << 4) /* Bit 4: PLL0 clock enable */ + /* Bit 5: Reserved */ +#define PLL0USB_CTRL_FRM (1 << 6) /* Bit 6: Free running mode */ + /* Bits 7-10: Reserved */ +#define PLL0USB_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define PLL0USB_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define PLL0USB_CTRL_CLKSEL_MASK (31 << PLL0USB_CTRL_CLKSEL_SHIFT) +# define PLL0USB_CLKSEL_32KHZOSC (0 << PLL0USB_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define PLL0USB_CLKSEL_IRC (1 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define PLL0USB_CLKSEL_ENET_RXCLK (2 << PLL0USB_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define PLL0USB_CLKSEL_ENET_TXCLK (3 << PLL0USB_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define PLL0USB_CLKSEL_GPCLKIN (4 << PLL0USB_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define PLL0USB_CLKSEL_XTAL (6 << PLL0USB_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define PLL0USB_CLKSEL_PLL1 (9 << PLL0USB_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define PLL0USB_CLKSEL_IDIVA (12 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define PLL0USB_CLKSEL_IDIVB (13 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define PLL0USB_CLKSEL_IDIVC (14 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define PLL0USB_CLKSEL_IDIVD (15 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define PLL0USB_CLKSEL_IDIVE (16 << PLL0USB_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* PLL0USB M-divider register */ -#define PLL0USB_MDIV_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */ -#define PLL0USB_MDIV_MDEC_MASK (0x1ffff << PLL0USB_MDIV_MDEC_SHIFT) -# define PLL0USB_MDIV_MDEC(n) ((n) << PLL0USB_MDIV_MDEC_SHIFT) -#define PLL0USB_MDIV_SELP_SHIFT (17) /* Bits 17-21: Bandwidth select P value */ -#define PLL0USB_MDIV_SELP_MASK (0x1f << PLL0USB_MDIV_SELP_SHIFT) -# define PLL0USB_MDIV_SELP(n) ((n) << PLL0USB_MDIV_SELP_SHIFT) -#define PLL0USB_MDIV_SELI_SHIFT (22) /* Bits 22-27: Bandwidth select I value */ -#define PLL0USB_MDIV_SELI_MASK (0x3f << PLL0USB_MDIV_SELI_SHIFT) -# define PLL0USB_MDIV_SELI(n) ((n) << PLL0USB_MDIV_SELI_SHIFT) -#define PLL0USB_MDIV_SELR_SHIFT (28) /* Bits 28-31: Bandwidth select R value */ -#define PLL0USB_MDIV_SELR_MASK (15 << PLL0USB_MDIV_SELR_SHIFT) -# define PLL0USB_MDIV_SELR(n) ((n) << PLL0USB_MDIV_SELR_SHIFT) +#define PLL0USB_MDIV_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */ +#define PLL0USB_MDIV_MDEC_MASK (0x1ffff << PLL0USB_MDIV_MDEC_SHIFT) +# define PLL0USB_MDIV_MDEC(n) ((n) << PLL0USB_MDIV_MDEC_SHIFT) +#define PLL0USB_MDIV_SELP_SHIFT (17) /* Bits 17-21: Bandwidth select P value */ +#define PLL0USB_MDIV_SELP_MASK (0x1f << PLL0USB_MDIV_SELP_SHIFT) +# define PLL0USB_MDIV_SELP(n) ((n) << PLL0USB_MDIV_SELP_SHIFT) +#define PLL0USB_MDIV_SELI_SHIFT (22) /* Bits 22-27: Bandwidth select I value */ +#define PLL0USB_MDIV_SELI_MASK (0x3f << PLL0USB_MDIV_SELI_SHIFT) +# define PLL0USB_MDIV_SELI(n) ((n) << PLL0USB_MDIV_SELI_SHIFT) +#define PLL0USB_MDIV_SELR_SHIFT (28) /* Bits 28-31: Bandwidth select R value */ +#define PLL0USB_MDIV_SELR_MASK (15 << PLL0USB_MDIV_SELR_SHIFT) +# define PLL0USB_MDIV_SELR(n) ((n) << PLL0USB_MDIV_SELR_SHIFT) /* PLL0USB N/P-divider register */ -#define PLL0USB_NP_DIV_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient value */ -#define PLL0USB_NP_DIV_PDEC_MASK (0x7f << PLL0USB_NP_DIV_PDEC_SHIFT) -# define PLL0USB_NP_DIV_PDEC(n) ((n) << PLL0USB_NP_DIV_PDEC_SHIFT) - /* Bits 7-11: Reserved */ -#define PLL0USB_NP_DIV_NDEC_SHIFT (12) /* Bits 12-21: Decoded N-divider coefficient value */ -#define PLL0USB_NP_DIV_NDEC_MASK (0x3ff << PLL0USB_NP_DIV_NDEC_SHIFT) -# define PLL0USB_NP_DIV_NDEC(n) ((n) << PLL0USB_NP_DIV_NDEC_SHIFT) - /* Bits 22-31: Reserved */ +#define PLL0USB_NP_DIV_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient value */ +#define PLL0USB_NP_DIV_PDEC_MASK (0x7f << PLL0USB_NP_DIV_PDEC_SHIFT) +# define PLL0USB_NP_DIV_PDEC(n) ((n) << PLL0USB_NP_DIV_PDEC_SHIFT) + /* Bits 7-11: Reserved */ +#define PLL0USB_NP_DIV_NDEC_SHIFT (12) /* Bits 12-21: Decoded N-divider coefficient value */ +#define PLL0USB_NP_DIV_NDEC_MASK (0x3ff << PLL0USB_NP_DIV_NDEC_SHIFT) +# define PLL0USB_NP_DIV_NDEC(n) ((n) << PLL0USB_NP_DIV_NDEC_SHIFT) + /* Bits 22-31: Reserved */ /* PLL0AUDIO status register */ -#define PLL0AUDIO_STAT_LOCK (1 << 0) /* Bit 0: PLL0 lock indicator */ -#define PLL0AUDIO_STAT_FR (1 << 1) /* Bit 1: PLL0 free running indicator */ - /* Bits 2-31: Reserved */ +#define PLL0AUDIO_STAT_LOCK (1 << 0) /* Bit 0: PLL0 lock indicator */ +#define PLL0AUDIO_STAT_FR (1 << 1) /* Bit 1: PLL0 free running indicator */ + /* Bits 2-31: Reserved */ /* PLL0AUDIO control register */ -#define PLL0AUDIO_CTRL_PD (1 << 0) /* Bit 0: PLL0 power down */ -#define PLL0AUDIO_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */ -#define PLL0AUDIO_CTRL_DIRECTI (1 << 2) /* Bit 2: PLL0 direct input */ -#define PLL0AUDIO_CTRL_DIRECTO (1 << 3) /* Bit 3: PLL0 direct output */ -#define PLL0AUDIO_CTRL_CLKEN (1 << 4) /* Bit 4: PLL0 clock enable */ - /* Bit 5: Reserved */ -#define PLL0AUDIO_CTRL_FRM (1 << 6) /* Bit 6: Free running mode */ - /* Bits 7-10: Reserved */ -#define PLL0AUDIO_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - -#define PLL0AUDIO_CTRL_PLLFRACTREQ (1 << 12) /* Bit 12: Fractional PLL word write request */ -#define PLL0AUDIO_CTRL_SELEXT (1 << 13) /* Bit 13: Select fractional divider */ -#define PLL0AUDIO_CTRL_MODPD (1 << 14) /* Bit 14: Sigma-Delta modulator power-down */ - /* Bits 15-23: Reserved */ -#define PLL0AUDIO_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define PLL0AUDIO_CTRL_CLKSEL_MASK (31 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) -# define PLL0AUDIO_CLKSEL_32KHZOSC (0 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define PLL0AUDIO_CLKSEL_IRC (1 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define PLL0AUDIO_CLKSEL_ENET_RXCLK (2 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define PLL0AUDIO_CLKSEL_ENET_TXCLK (3 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define PLL0AUDIO_CLKSEL_GPCLKIN (4 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define PLL0AUDIO_CLKSEL_XTAL (6 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define PLL0AUDIO_CLKSEL_PLL1 (9 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define PLL0AUDIO_CLKSEL_IDIVA (12 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define PLL0AUDIO_CLKSEL_IDIVB (13 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define PLL0AUDIO_CLKSEL_IDIVC (14 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define PLL0AUDIO_CLKSEL_IDIVD (15 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define PLL0AUDIO_CLKSEL_IDIVE (16 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define PLL0AUDIO_CTRL_PD (1 << 0) /* Bit 0: PLL0 power down */ +#define PLL0AUDIO_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */ +#define PLL0AUDIO_CTRL_DIRECTI (1 << 2) /* Bit 2: PLL0 direct input */ +#define PLL0AUDIO_CTRL_DIRECTO (1 << 3) /* Bit 3: PLL0 direct output */ +#define PLL0AUDIO_CTRL_CLKEN (1 << 4) /* Bit 4: PLL0 clock enable */ + /* Bit 5: Reserved */ +#define PLL0AUDIO_CTRL_FRM (1 << 6) /* Bit 6: Free running mode */ + /* Bits 7-10: Reserved */ +#define PLL0AUDIO_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + +#define PLL0AUDIO_CTRL_PLLFRACTREQ (1 << 12) /* Bit 12: Fractional PLL word write request */ +#define PLL0AUDIO_CTRL_SELEXT (1 << 13) /* Bit 13: Select fractional divider */ +#define PLL0AUDIO_CTRL_MODPD (1 << 14) /* Bit 14: Sigma-Delta modulator power-down */ + /* Bits 15-23: Reserved */ +#define PLL0AUDIO_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define PLL0AUDIO_CTRL_CLKSEL_MASK (31 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) +# define PLL0AUDIO_CLKSEL_32KHZOSC (0 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define PLL0AUDIO_CLKSEL_IRC (1 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define PLL0AUDIO_CLKSEL_ENET_RXCLK (2 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define PLL0AUDIO_CLKSEL_ENET_TXCLK (3 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define PLL0AUDIO_CLKSEL_GPCLKIN (4 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define PLL0AUDIO_CLKSEL_XTAL (6 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define PLL0AUDIO_CLKSEL_PLL1 (9 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define PLL0AUDIO_CLKSEL_IDIVA (12 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define PLL0AUDIO_CLKSEL_IDIVB (13 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define PLL0AUDIO_CLKSEL_IDIVC (14 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define PLL0AUDIO_CLKSEL_IDIVD (15 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define PLL0AUDIO_CLKSEL_IDIVE (16 << PLL0AUDIO_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* PLL0AUDIO M-divider */ -#define PLL0AUDIO_MDIV_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */ -#define PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << PLL0AUDIO_MDIV_MDEC_SHIFT) -# define PLL0AUDIO_MDIV_MDEC(n) ((n) << PLL0AUDIO_MDIV_MDEC_SHIFT) - /* Bits 17-31: Reserved */ +#define PLL0AUDIO_MDIV_MDEC_SHIFT (0) /* Bits 0-16: Decoded M-divider coefficient value (1-131071) */ +#define PLL0AUDIO_MDIV_MDEC_MASK (0x1ffff << PLL0AUDIO_MDIV_MDEC_SHIFT) +# define PLL0AUDIO_MDIV_MDEC(n) ((n) << PLL0AUDIO_MDIV_MDEC_SHIFT) + /* Bits 17-31: Reserved */ /* PLL0AUDIO N/P-divider */ -#define PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient value */ -#define PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << PLL0AUDIO_NP_DIV_PDEC_SHIFT) -# define PLL0AUDIO_NP_DIV_PDEC(n) ((n) << PLL0AUDIO_NP_DIV_PDEC_SHIFT) - /* Bits 7-11: Reserved */ -#define PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) /* Bits 12-21: Decoded N-divider coefficient value */ -#define PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << PLL0AUDIO_NP_DIV_NDEC_SHIFT) -# define PLL0AUDIO_NP_DIV_NDEC(n) ((n) << PLL0AUDIO_NP_DIV_NDEC_SHIFT) - /* Bits 22-31: Reserved */ +#define PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) /* Bits 0-6: Decoded P-divider coefficient value */ +#define PLL0AUDIO_NP_DIV_PDEC_MASK (0x7f << PLL0AUDIO_NP_DIV_PDEC_SHIFT) +# define PLL0AUDIO_NP_DIV_PDEC(n) ((n) << PLL0AUDIO_NP_DIV_PDEC_SHIFT) + /* Bits 7-11: Reserved */ +#define PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) /* Bits 12-21: Decoded N-divider coefficient value */ +#define PLL0AUDIO_NP_DIV_NDEC_MASK (0x3ff << PLL0AUDIO_NP_DIV_NDEC_SHIFT) +# define PLL0AUDIO_NP_DIV_NDEC(n) ((n) << PLL0AUDIO_NP_DIV_NDEC_SHIFT) + /* Bits 22-31: Reserved */ /* PLL0AUDIO fractional */ -#define PLL0AUDIO_FRAC_CTRL_SHIFT (0) /* Bits 0-21: Decoded P-divider coefficient value */ -#define PLL0AUDIO_FRAC_CTRL_MASK (0x3fffff << PLL0AUDIO_FRAC_CTRL_SHIFT) -# define PLL0AUDIO_FRA_CCTRL(n) ((n) << PLL0AUDIO_FRAC_CTRL_SHIFT) - /* Bits 22-31: Reserved */ +#define PLL0AUDIO_FRAC_CTRL_SHIFT (0) /* Bits 0-21: Decoded P-divider coefficient value */ +#define PLL0AUDIO_FRAC_CTRL_MASK (0x3fffff << PLL0AUDIO_FRAC_CTRL_SHIFT) +# define PLL0AUDIO_FRA_CCTRL(n) ((n) << PLL0AUDIO_FRAC_CTRL_SHIFT) + /* Bits 22-31: Reserved */ /* PLL1 status register */ -#define PLL1_STAT_LOCK (1 << 0) /* Bit 0: PLL1 lock indicator */ - /* Bits 1-31: Reserved */ +#define PLL1_STAT_LOCK (1 << 0) /* Bit 0: PLL1 lock indicator */ + /* Bits 1-31: Reserved */ /* PLL1 control register */ -#define PLL1_CTRL_PD (1 << 0) /* Bit 0: PLL1 power down */ -#define PLL1_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */ - /* Bits 2-5: Reserved */ -#define PLL1_CTRL_FBSEL (1 << 6) /* Bit 6: PLL1 feedback select */ -#define PLL1_CTRL_DIRECT (1 << 7) /* Bit 7: PLL1 direct CCO output */ - -#define PLL1_CTRL_PSEL_SHIFT (8) /* Bits 8-9: Post-divider division ratio P */ -#define PLL1_CTRL_PSEL_MASK (3 << PLL1_CTRL_PSEL_SHIFT) -# define PLL1_CTRL_PSEL_DIV1 (0 << PLL1_CTRL_PSEL_SHIFT) -# define PLL1_CTRL_PSEL_DIV2 (1 << PLL1_CTRL_PSEL_SHIFT) -# define PLL1_CTRL_PSEL_DIV4 (2 << PLL1_CTRL_PSEL_SHIFT) -# define PLL1_CTRL_PSEL_DIV8 (3 << PLL1_CTRL_PSEL_SHIFT) - /* Bit 10: Reserved */ -#define PLL1_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ -#define PLL1_CTRL_NSEL_SHIFT (12) /* Bits 12-13: Pre-divider division ratio N */ -#define PLL1_CTRL_NSEL_MASK (3 << PLL1_CTRL_NSEL_SHIFT) -# define PLL1_CTRL_NSEL_DIV1 (0 << PLL1_CTRL_NSEL_SHIFT) -# define PLL1_CTRL_NSEL_DIV2 (1 << PLL1_CTRL_NSEL_SHIFT) -# define PLL1_CTRL_NSEL_DIV3 (2 << PLL1_CTRL_NSEL_SHIFT) -# define PLL1_CTRL_NSEL_DIV4 (3 << PLL1_CTRL_NSEL_SHIFT) - /* Bits 14-15: Reserved */ -#define PLL1_CTRL_MSEL_SHIFT (16) /* Bits 16-17: Feedback-divider division ratio M */ -#define PLL1_CTRL_MSEL_MASK (3 << PLL1_CTRL_MSEL_SHIFT) -# define PLL1_CTRL_MSEL_DIV(n) (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */ -#define PLL1_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define PLL1_CTRL_CLKSEL_MASK (31 << PLL1_CTRL_CLKSEL_SHIFT) -# define PLL1_CLKSEL_32KHZOSC (0 << PLL1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define PLL1_CLKSEL_IRC (1 << PLL1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define PLL1_CLKSEL_ENET_RXCLK (2 << PLL1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define PLL1_CLKSEL_ENET_TXCLK (3 << PLL1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define PLL1_CLKSEL_GPCLKIN (4 << PLL1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define PLL1_CLKSEL_XTAL (6 << PLL1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define PLL1_CLKSEL_PLL0USB (7 << PLL1_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define PLL1_CLKSEL_PLL0AUDIO (8 << PLL1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define PLL1_CLKSEL_IDIVA (12 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define PLL1_CLKSEL_IDIVB (13 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define PLL1_CLKSEL_IDIVC (14 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define PLL1_CLKSEL_IDIVD (15 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define PLL1_CLKSEL_IDIVE (16 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define PLL1_CTRL_PD (1 << 0) /* Bit 0: PLL1 power down */ +#define PLL1_CTRL_BYPASS (1 << 1) /* Bit 1: Input clock bypass control */ + /* Bits 2-5: Reserved */ +#define PLL1_CTRL_FBSEL (1 << 6) /* Bit 6: PLL1 feedback select */ +#define PLL1_CTRL_DIRECT (1 << 7) /* Bit 7: PLL1 direct CCO output */ + +#define PLL1_CTRL_PSEL_SHIFT (8) /* Bits 8-9: Post-divider division ratio P */ +#define PLL1_CTRL_PSEL_MASK (3 << PLL1_CTRL_PSEL_SHIFT) +# define PLL1_CTRL_PSEL_DIV1 (0 << PLL1_CTRL_PSEL_SHIFT) +# define PLL1_CTRL_PSEL_DIV2 (1 << PLL1_CTRL_PSEL_SHIFT) +# define PLL1_CTRL_PSEL_DIV4 (2 << PLL1_CTRL_PSEL_SHIFT) +# define PLL1_CTRL_PSEL_DIV8 (3 << PLL1_CTRL_PSEL_SHIFT) + /* Bit 10: Reserved */ +#define PLL1_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ +#define PLL1_CTRL_NSEL_SHIFT (12) /* Bits 12-13: Pre-divider division ratio N */ +#define PLL1_CTRL_NSEL_MASK (3 << PLL1_CTRL_NSEL_SHIFT) +# define PLL1_CTRL_NSEL_DIV1 (0 << PLL1_CTRL_NSEL_SHIFT) +# define PLL1_CTRL_NSEL_DIV2 (1 << PLL1_CTRL_NSEL_SHIFT) +# define PLL1_CTRL_NSEL_DIV3 (2 << PLL1_CTRL_NSEL_SHIFT) +# define PLL1_CTRL_NSEL_DIV4 (3 << PLL1_CTRL_NSEL_SHIFT) + /* Bits 14-15: Reserved */ +#define PLL1_CTRL_MSEL_SHIFT (16) /* Bits 16-17: Feedback-divider division ratio M */ +#define PLL1_CTRL_MSEL_MASK (3 << PLL1_CTRL_MSEL_SHIFT) +# define PLL1_CTRL_MSEL_DIV(n) (((n)-1) << PLL1_CTRL_MSEL_SHIFT) /* n=1..256 */ +#define PLL1_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define PLL1_CTRL_CLKSEL_MASK (31 << PLL1_CTRL_CLKSEL_SHIFT) +# define PLL1_CLKSEL_32KHZOSC (0 << PLL1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define PLL1_CLKSEL_IRC (1 << PLL1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define PLL1_CLKSEL_ENET_RXCLK (2 << PLL1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define PLL1_CLKSEL_ENET_TXCLK (3 << PLL1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define PLL1_CLKSEL_GPCLKIN (4 << PLL1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define PLL1_CLKSEL_XTAL (6 << PLL1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define PLL1_CLKSEL_PLL0USB (7 << PLL1_CTRL_CLKSEL_SHIFT) /* PLL0USB */ +# define PLL1_CLKSEL_PLL0AUDIO (8 << PLL1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define PLL1_CLKSEL_IDIVA (12 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define PLL1_CLKSEL_IDIVB (13 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define PLL1_CLKSEL_IDIVC (14 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define PLL1_CLKSEL_IDIVD (15 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define PLL1_CLKSEL_IDIVE (16 << PLL1_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Integer divider A control register */ -#define IDIVA_CTRL_PD (1 << 0) /* Bit 0: Integer divider A power down */ - /* Bit 1: Reserved */ -#define IDIVA_CTRL_IDIV_SHIFT (2) /* Bits 2-3: Integer divider A divider values (1/(IDIV + 1)) */ -#define IDIVA_CTRL_IDIV_MASK (3 << IDIVA_CTRL_IDIV_SHIFT) -# define IDIVA_CTRL_IDIV(n) (((n)-1) << IDIVA_CTRL_IDIV_SHIFT) /* n=1..4 */ - /* Bits 4-10: Reserved */ -#define IDIVA_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define IDIVA_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define IDIVA_CTRL_CLKSEL_MASK (31 << IDIVA_CTRL_CLKSEL_SHIFT) -# define IDIVA_CLKSEL_32KHZOSC (0 << IDIVA_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define IDIVA_CLKSEL_IRC (1 << IDIVA_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define IDIVA_CLKSEL_ENET_RXCLK (2 << IDIVA_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define IDIVA_CLKSEL_ENET_TXCLK (3 << IDIVA_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define IDIVA_CLKSEL_GPCLKIN (4 << IDIVA_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define IDIVA_CLKSEL_XTAL (6 << IDIVA_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define IDIVA_CLKSEL_PLL0USB (7 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define IDIVA_CLKSEL_PLL0AUDIO (8 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define IDIVA_CLKSEL_PLL1 (9 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL1 */ - /* Bits 29-31: Reserved */ +#define IDIVA_CTRL_PD (1 << 0) /* Bit 0: Integer divider A power down */ + /* Bit 1: Reserved */ +#define IDIVA_CTRL_IDIV_SHIFT (2) /* Bits 2-3: Integer divider A divider values (1/(IDIV + 1)) */ +#define IDIVA_CTRL_IDIV_MASK (3 << IDIVA_CTRL_IDIV_SHIFT) +# define IDIVA_CTRL_IDIV(n) (((n)-1) << IDIVA_CTRL_IDIV_SHIFT) /* n=1..4 */ + /* Bits 4-10: Reserved */ +#define IDIVA_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define IDIVA_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define IDIVA_CTRL_CLKSEL_MASK (31 << IDIVA_CTRL_CLKSEL_SHIFT) +# define IDIVA_CLKSEL_32KHZOSC (0 << IDIVA_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define IDIVA_CLKSEL_IRC (1 << IDIVA_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define IDIVA_CLKSEL_ENET_RXCLK (2 << IDIVA_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define IDIVA_CLKSEL_ENET_TXCLK (3 << IDIVA_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define IDIVA_CLKSEL_GPCLKIN (4 << IDIVA_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define IDIVA_CLKSEL_XTAL (6 << IDIVA_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define IDIVA_CLKSEL_PLL0USB (7 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL0USB */ +# define IDIVA_CLKSEL_PLL0AUDIO (8 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define IDIVA_CLKSEL_PLL1 (9 << IDIVA_CTRL_CLKSEL_SHIFT) /* PLL1 */ + /* Bits 29-31: Reserved */ /* Integer divider B/C/D control register */ -#define IDIVBCD_CTRL_PD (1 << 0) /* Bit 0: Integer divider power down */ - /* Bit 1: Reserved */ -#define IDIVBCD_CTRL_IDIV_SHIFT (2) /* Bits 2-5: Integer divider A divider values (1/(IDIV + 1)) */ -#define IDIVBCD_CTRL_IDIV_MASK (15 << IDIVBCD_CTRL_IDIV_SHIFT) -# define IDIVBCD_CTRL_IDIV_DIV(n) (((n)-1) << IDIVBCD_CTRL_IDIV_SHIFT) /* n=1..16 */ - /* Bits 6-10: Reserved */ -#define IDIVBCD_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define IDIVBCD_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define IDIVBCD_CTRL_CLKSEL_MASK (31 << IDIVBCD_CTRL_CLKSEL_SHIFT) -# define IDIVBCD_CLKSEL_32KHZOSC (0 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define IDIVBCD_CLKSEL_IRC (1 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define IDIVBCD_CLKSEL_ENET_RXCLK (2 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define IDIVBCD_CLKSEL_ENET_TXCLK (3 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define IDIVBCD_CLKSEL_GPCLKIN (4 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define IDIVBCD_CLKSEL_XTAL (6 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define IDIVBCD_CLKSEL_PLL0AUDIO (8 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define IDIVBCD_CLKSEL_PLL1 (9 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define IDIVBCD_CLKSEL_IDIVA (12 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IDIVA */ - /* Bits 29-31: Reserved */ +#define IDIVBCD_CTRL_PD (1 << 0) /* Bit 0: Integer divider power down */ + /* Bit 1: Reserved */ +#define IDIVBCD_CTRL_IDIV_SHIFT (2) /* Bits 2-5: Integer divider A divider values (1/(IDIV + 1)) */ +#define IDIVBCD_CTRL_IDIV_MASK (15 << IDIVBCD_CTRL_IDIV_SHIFT) +# define IDIVBCD_CTRL_IDIV_DIV(n) (((n)-1) << IDIVBCD_CTRL_IDIV_SHIFT) /* n=1..16 */ + /* Bits 6-10: Reserved */ +#define IDIVBCD_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define IDIVBCD_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define IDIVBCD_CTRL_CLKSEL_MASK (31 << IDIVBCD_CTRL_CLKSEL_SHIFT) +# define IDIVBCD_CLKSEL_32KHZOSC (0 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define IDIVBCD_CLKSEL_IRC (1 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define IDIVBCD_CLKSEL_ENET_RXCLK (2 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define IDIVBCD_CLKSEL_ENET_TXCLK (3 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define IDIVBCD_CLKSEL_GPCLKIN (4 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define IDIVBCD_CLKSEL_XTAL (6 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define IDIVBCD_CLKSEL_PLL0AUDIO (8 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define IDIVBCD_CLKSEL_PLL1 (9 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define IDIVBCD_CLKSEL_IDIVA (12 << IDIVBCD_CTRL_CLKSEL_SHIFT) /* IDIVA */ + /* Bits 29-31: Reserved */ /* Integer divider E control register */ -#define IDIVE_CTRL_PD (1 << 0) /* Bit 0: Integer divider E power down */ - /* Bit 1: Reserved */ -#define IDIVE_CTRL_IDIV_SHIFT (2) /* Bits 2-9: Integer divider A divider values (1/(IDIV + 1)) */ -#define IDIVE_CTRL_IDIV_MASK (0xff << IDIVE_CTRL_IDIV_SHIFT) -# define IDIVE_CTRL_IDIV_DIV(n) (((n)-1) << IDIVE_CTRL_IDIV_SHIFT) /* n=1..256 */ - /* Bit 10: Reserved */ -#define IDIVE_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define IDIVE_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define IDIVE_CTRL_CLKSEL_MASK (31 << IDIVE_CTRL_CLKSEL_SHIFT) -# define IDIVE_CLKSEL_32KHZOSC (0 << IDIVE_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define IDIVE_CLKSEL_IRC (1 << IDIVE_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define IDIVE_CLKSEL_ENET_RXCLK (2 << IDIVE_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define IDIVE_CLKSEL_ENET_TXCLK (3 << IDIVE_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define IDIVE_CLKSEL_GPCLKIN (4 << IDIVE_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define IDIVE_CLKSEL_XTAL (6 << IDIVE_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define IDIVE_CLKSEL_PLL0AUDIO (8 << IDIVE_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define IDIVE_CLKSEL_PLL1 (9 << IDIVE_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define IDIVE_CLKSEL_IDIVA (12 << IDIVE_CTRL_CLKSEL_SHIFT) /* IDIVA */ - /* Bits 29-31: Reserved */ +#define IDIVE_CTRL_PD (1 << 0) /* Bit 0: Integer divider E power down */ + /* Bit 1: Reserved */ +#define IDIVE_CTRL_IDIV_SHIFT (2) /* Bits 2-9: Integer divider A divider values (1/(IDIV + 1)) */ +#define IDIVE_CTRL_IDIV_MASK (0xff << IDIVE_CTRL_IDIV_SHIFT) +# define IDIVE_CTRL_IDIV_DIV(n) (((n)-1) << IDIVE_CTRL_IDIV_SHIFT) /* n=1..256 */ + /* Bit 10: Reserved */ +#define IDIVE_CTRL_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define IDIVE_CTRL_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define IDIVE_CTRL_CLKSEL_MASK (31 << IDIVE_CTRL_CLKSEL_SHIFT) +# define IDIVE_CLKSEL_32KHZOSC (0 << IDIVE_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define IDIVE_CLKSEL_IRC (1 << IDIVE_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define IDIVE_CLKSEL_ENET_RXCLK (2 << IDIVE_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define IDIVE_CLKSEL_ENET_TXCLK (3 << IDIVE_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define IDIVE_CLKSEL_GPCLKIN (4 << IDIVE_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define IDIVE_CLKSEL_XTAL (6 << IDIVE_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define IDIVE_CLKSEL_PLL0AUDIO (8 << IDIVE_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define IDIVE_CLKSEL_PLL1 (9 << IDIVE_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define IDIVE_CLKSEL_IDIVA (12 << IDIVE_CTRL_CLKSEL_SHIFT) /* IDIVA */ + /* Bits 29-31: Reserved */ /* Output stage 0 control register (BASE_SAFE_CLK) */ -#define BASE_SAFE_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_SAFE_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_SAFE_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_SAFE_CLK_CLKSEL_MASK (31 << BASE_SAFE_CLK_CLKSEL_SHIFT) -# define BASE_SAFE_CLKSEL_IRC (1 << BASE_SAFE_CLK_CLKSEL_SHIFT) /* IRC (default) */ - /* Bits 29-31: Reserved */ +#define BASE_SAFE_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_SAFE_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_SAFE_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_SAFE_CLK_CLKSEL_MASK (31 << BASE_SAFE_CLK_CLKSEL_SHIFT) +# define BASE_SAFE_CLKSEL_IRC (1 << BASE_SAFE_CLK_CLKSEL_SHIFT) /* IRC (default) */ + /* Bits 29-31: Reserved */ /* Output stage 1 control register (BASE_USB0_CLK) */ -#define BASE_USB0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_USB0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_USB0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_USB0_CLK_CLKSEL_MASK (31 << BASE_USB0_CLK_CLKSEL_SHIFT) -# define BASE_USB0_CLKSEL_PLL0USB (7 << BASE_USB0_CLK_CLKSEL_SHIFT) /* PLL0USB (default) */ - /* Bits 29-31: Reserved */ +#define BASE_USB0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_USB0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_USB0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_USB0_CLK_CLKSEL_MASK (31 << BASE_USB0_CLK_CLKSEL_SHIFT) +# define BASE_USB0_CLKSEL_PLL0USB (7 << BASE_USB0_CLK_CLKSEL_SHIFT) /* PLL0USB (default) */ + /* Bits 29-31: Reserved */ /* Output stage 2 control register (BASE_PERIPH_CLK) */ -#define BASE_PERIPH_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_PERIPH_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_PERIPH_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_PERIPH_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_PERIPH_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_PERIPH_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ #define BASE_PERIPH_CLK_CLKSEL_MASK (31 << BASE_PERIPH_CLK_CLKSEL_SHIFT) # define BASE_PERIPH_CLKSEL_32KHZOSC (0 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ # define BASE_PERIPH_CLKSEL_IRC (1 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IRC (default) */ @@ -435,398 +435,398 @@ # define BASE_PERIPH_CLKSEL_IDIVC (14 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVC */ # define BASE_PERIPH_CLKSEL_IDIVD (15 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVD */ # define BASE_PERIPH_CLKSEL_IDIVE (16 << BASE_PERIPH_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ + /* Bits 29-31: Reserved */ /* Output stage 3 control register (BASE_USB1_CLK) */ -#define BASE_USB1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_USB1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_USB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_USB1_CLK_CLKSEL_MASK (31 << BASE_USB1_CLK_CLKSEL_SHIFT) -# define BASE_USB1_CLKSEL_32KHZOSC (0 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_USB1_CLKSEL_IRC (1 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_USB1_CLKSEL_ENET_RXCLK (2 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_USB1_CLKSEL_ENET_TXCLK (3 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_USB1_CLKSEL_GPCLKIN (4 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_USB1_CLKSEL_XTAL (6 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_USB1_CLKSEL_PLL0USB (7 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define BASE_USB1_CLKSEL_PLL0AUDIO (8 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_USB1_CLKSEL_PLL1 (9 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_USB1_CLKSEL_IDIVA (12 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_USB1_CLKSEL_IDIVB (13 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_USB1_CLKSEL_IDIVC (14 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_USB1_CLKSEL_IDIVD (15 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_USB1_CLKSEL_IDIVE (16 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_USB1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_USB1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_USB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_USB1_CLK_CLKSEL_MASK (31 << BASE_USB1_CLK_CLKSEL_SHIFT) +# define BASE_USB1_CLKSEL_32KHZOSC (0 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USB1_CLKSEL_IRC (1 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USB1_CLKSEL_ENET_RXCLK (2 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USB1_CLKSEL_ENET_TXCLK (3 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USB1_CLKSEL_GPCLKIN (4 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USB1_CLKSEL_XTAL (6 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USB1_CLKSEL_PLL0USB (7 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0USB */ +# define BASE_USB1_CLKSEL_PLL0AUDIO (8 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USB1_CLKSEL_PLL1 (9 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USB1_CLKSEL_IDIVA (12 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USB1_CLKSEL_IDIVB (13 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USB1_CLKSEL_IDIVC (14 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USB1_CLKSEL_IDIVD (15 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USB1_CLKSEL_IDIVE (16 << BASE_USB1_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 4 control register (BASE_M4_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_M4_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_M4_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_M4_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_M4_CLK_CLKSEL_MASK (31 << BASE_M4_CLK_CLKSEL_SHIFT) -# define BASE_M4_CLKSEL_32KHZOSC (0 << BASE_M4_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_M4_CLKSEL_IRC (1 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_M4_CLKSEL_ENET_RXCLK (2 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_M4_CLKSEL_ENET_TXCLK (3 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_M4_CLKSEL_GPCLKIN (4 << BASE_M4_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_M4_CLKSEL_XTAL (6 << BASE_M4_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_M4_CLKSEL_PLL0AUDIO (8 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_M4_CLKSEL_PLL1 (9 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_M4_CLKSEL_IDIVA (12 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_M4_CLKSEL_IDIVB (13 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_M4_CLKSEL_IDIVC (14 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_M4_CLKSEL_IDIVD (15 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_M4_CLKSEL_IDIVE (16 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_M4_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_M4_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_M4_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_M4_CLK_CLKSEL_MASK (31 << BASE_M4_CLK_CLKSEL_SHIFT) +# define BASE_M4_CLKSEL_32KHZOSC (0 << BASE_M4_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_M4_CLKSEL_IRC (1 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_M4_CLKSEL_ENET_RXCLK (2 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_M4_CLKSEL_ENET_TXCLK (3 << BASE_M4_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_M4_CLKSEL_GPCLKIN (4 << BASE_M4_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_M4_CLKSEL_XTAL (6 << BASE_M4_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_M4_CLKSEL_PLL0AUDIO (8 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_M4_CLKSEL_PLL1 (9 << BASE_M4_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_M4_CLKSEL_IDIVA (12 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_M4_CLKSEL_IDIVB (13 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_M4_CLKSEL_IDIVC (14 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_M4_CLKSEL_IDIVD (15 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_M4_CLKSEL_IDIVE (16 << BASE_M4_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 5 control register (BASE_SPIFI_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_SPIFI_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_SPIFI_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_SPIFI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_SPIFI_CLK_CLKSEL_MASK (31 << BASE_SPIFI_CLK_CLKSEL_SHIFT) -# define BASE_SPIFI_CLKSEL_32KHZOSC (0 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SPIFI_CLKSEL_IRC (1 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SPIFI_CLKSEL_ENET_RXCLK (2 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SPIFI_CLKSEL_ENET_TXCLK (3 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SPIFI_CLKSEL_GPCLKIN (4 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SPIFI_CLKSEL_XTAL (6 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SPIFI_CLKSEL_PLL0AUDIO (8 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SPIFI_CLKSEL_PLL1 (9 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SPIFI_CLKSEL_IDIVA (12 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SPIFI_CLKSEL_IDIVB (13 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SPIFI_CLKSEL_IDIVC (14 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SPIFI_CLKSEL_IDIVD (15 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SPIFI_CLKSEL_IDIVE (16 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_SPIFI_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_SPIFI_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_SPIFI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_SPIFI_CLK_CLKSEL_MASK (31 << BASE_SPIFI_CLK_CLKSEL_SHIFT) +# define BASE_SPIFI_CLKSEL_32KHZOSC (0 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SPIFI_CLKSEL_IRC (1 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SPIFI_CLKSEL_ENET_RXCLK (2 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SPIFI_CLKSEL_ENET_TXCLK (3 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SPIFI_CLKSEL_GPCLKIN (4 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SPIFI_CLKSEL_XTAL (6 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SPIFI_CLKSEL_PLL0AUDIO (8 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SPIFI_CLKSEL_PLL1 (9 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SPIFI_CLKSEL_IDIVA (12 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SPIFI_CLKSEL_IDIVB (13 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SPIFI_CLKSEL_IDIVC (14 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SPIFI_CLKSEL_IDIVD (15 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SPIFI_CLKSEL_IDIVE (16 << BASE_SPIFI_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 6 control register (BASE_SPI_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_SPI_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_SPI_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_SPI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_SPI_CLK_CLKSEL_MASK (31 << BASE_SPI_CLK_CLKSEL_SHIFT) -# define BASE_SPI_CLKSEL_32KHZOSC (0 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SPI_CLKSEL_IRC (1 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SPI_CLKSEL_ENET_RXCLK (2 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SPI_CLKSEL_ENET_TXCLK (3 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SPI_CLKSEL_GPCLKIN (4 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SPI_CLKSEL_XTAL (6 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SPI_CLKSEL_PLL0AUDIO (8 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SPI_CLKSEL_PLL1 (9 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SPI_CLKSEL_IDIVA (12 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SPI_CLKSEL_IDIVB (13 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SPI_CLKSEL_IDIVC (14 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SPI_CLKSEL_IDIVD (15 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SPI_CLKSEL_IDIVE (16 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_SPI_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_SPI_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_SPI_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_SPI_CLK_CLKSEL_MASK (31 << BASE_SPI_CLK_CLKSEL_SHIFT) +# define BASE_SPI_CLKSEL_32KHZOSC (0 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SPI_CLKSEL_IRC (1 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SPI_CLKSEL_ENET_RXCLK (2 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SPI_CLKSEL_ENET_TXCLK (3 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SPI_CLKSEL_GPCLKIN (4 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SPI_CLKSEL_XTAL (6 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SPI_CLKSEL_PLL0AUDIO (8 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SPI_CLKSEL_PLL1 (9 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SPI_CLKSEL_IDIVA (12 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SPI_CLKSEL_IDIVB (13 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SPI_CLKSEL_IDIVC (14 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SPI_CLKSEL_IDIVD (15 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SPI_CLKSEL_IDIVE (16 << BASE_SPI_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 7 control register (BASE_PHY_RX_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_PHYRX_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_PHYRX_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_PHYRX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_PHYRX_CLK_CLKSEL_MASK (31 << BASE_PHYRX_CLK_CLKSEL_SHIFT) -# define BASE_PHYRX_CLKSEL_32KHZOSC (0 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_PHYRX_CLKSEL_IRC (1 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_PHYRX_CLKSEL_ENET_RXCLK (2 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_PHYRX_CLKSEL_ENET_TXCLK (3 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_PHYRX_CLKSEL_GPCLKIN (4 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_PHYRX_CLKSEL_XTAL (6 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_PHYRX_CLKSEL_PLL0AUDIO (8 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_PHYRX_CLKSEL_PLL1 (9 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_PHYRX_CLKSEL_IDIVA (12 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_PHYRX_CLKSEL_IDIVB (13 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_PHYRX_CLKSEL_IDIVC (14 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_PHYRX_CLKSEL_IDIVD (15 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_PHYRX_CLKSEL_IDIVE (16 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_PHYRX_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_PHYRX_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_PHYRX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_PHYRX_CLK_CLKSEL_MASK (31 << BASE_PHYRX_CLK_CLKSEL_SHIFT) +# define BASE_PHYRX_CLKSEL_32KHZOSC (0 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_PHYRX_CLKSEL_IRC (1 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_PHYRX_CLKSEL_ENET_RXCLK (2 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_PHYRX_CLKSEL_ENET_TXCLK (3 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_PHYRX_CLKSEL_GPCLKIN (4 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_PHYRX_CLKSEL_XTAL (6 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_PHYRX_CLKSEL_PLL0AUDIO (8 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_PHYRX_CLKSEL_PLL1 (9 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_PHYRX_CLKSEL_IDIVA (12 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_PHYRX_CLKSEL_IDIVB (13 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_PHYRX_CLKSEL_IDIVC (14 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_PHYRX_CLKSEL_IDIVD (15 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_PHYRX_CLKSEL_IDIVE (16 << BASE_PHYRX_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 8 control register (BASE_PHY_TX_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_PHYTX_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_PHYTX_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_PHYTX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_PHYTX_CLK_CLKSEL_MASK (31 << BASE_PHYTX_CLK_CLKSEL_SHIFT) -# define BASE_PHYTX_CLKSEL_32KHZOSC (0 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_PHYTX_CLKSEL_IRC (1 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_PHYTX_CLKSEL_ENET_RXCLK (2 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_PHYTX_CLKSEL_ENET_TXCLK (3 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_PHYTX_CLKSEL_GPCLKIN (4 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_PHYTX_CLKSEL_XTAL (6 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_PHYTX_CLKSEL_PLL0AUDIO (8 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_PHYTX_CLKSEL_PLL1 (9 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_PHYTX_CLKSEL_IDIVA (12 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_PHYTX_CLKSEL_IDIVB (13 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_PHYTX_CLKSEL_IDIVC (14 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_PHYTX_CLKSEL_IDIVD (15 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_PHYTX_CLKSEL_IDIVE (16 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_PHYTX_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_PHYTX_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_PHYTX_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_PHYTX_CLK_CLKSEL_MASK (31 << BASE_PHYTX_CLK_CLKSEL_SHIFT) +# define BASE_PHYTX_CLKSEL_32KHZOSC (0 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_PHYTX_CLKSEL_IRC (1 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_PHYTX_CLKSEL_ENET_RXCLK (2 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_PHYTX_CLKSEL_ENET_TXCLK (3 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_PHYTX_CLKSEL_GPCLKIN (4 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_PHYTX_CLKSEL_XTAL (6 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_PHYTX_CLKSEL_PLL0AUDIO (8 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_PHYTX_CLKSEL_PLL1 (9 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_PHYTX_CLKSEL_IDIVA (12 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_PHYTX_CLKSEL_IDIVB (13 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_PHYTX_CLKSEL_IDIVC (14 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_PHYTX_CLKSEL_IDIVD (15 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_PHYTX_CLKSEL_IDIVE (16 << BASE_PHYTX_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 9 control register (BASE_APB1_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_APB1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_APB1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_APB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_APB1_CLK_CLKSEL_MASK (31 << BASE_APB1_CLK_CLKSEL_SHIFT) -# define BASE_APB1_CLKSEL_32KHZOSC (0 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_APB1_CLKSEL_IRC (1 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_APB1_CLKSEL_ENET_RXCLK (2 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_APB1_CLKSEL_ENET_TXCLK (3 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_APB1_CLKSEL_GPCLKIN (4 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_APB1_CLKSEL_XTAL (6 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_APB1_CLKSEL_PLL0AUDIO (8 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_APB1_CLKSEL_PLL1 (9 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_APB1_CLKSEL_IDIVA (12 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_APB1_CLKSEL_IDIVB (13 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_APB1_CLKSEL_IDIVC (14 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_APB1_CLKSEL_IDIVD (15 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_APB1_CLKSEL_IDIVE (16 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_APB1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_APB1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_APB1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_APB1_CLK_CLKSEL_MASK (31 << BASE_APB1_CLK_CLKSEL_SHIFT) +# define BASE_APB1_CLKSEL_32KHZOSC (0 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_APB1_CLKSEL_IRC (1 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_APB1_CLKSEL_ENET_RXCLK (2 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_APB1_CLKSEL_ENET_TXCLK (3 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_APB1_CLKSEL_GPCLKIN (4 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_APB1_CLKSEL_XTAL (6 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_APB1_CLKSEL_PLL0AUDIO (8 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_APB1_CLKSEL_PLL1 (9 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_APB1_CLKSEL_IDIVA (12 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_APB1_CLKSEL_IDIVB (13 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_APB1_CLKSEL_IDIVC (14 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_APB1_CLKSEL_IDIVD (15 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_APB1_CLKSEL_IDIVE (16 << BASE_APB1_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 11 control register (BASE_LCD_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_LCD_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_LCD_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_LCD_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_LCD_CLK_CLKSEL_MASK (31 << BASE_LCD_CLK_CLKSEL_SHIFT) -# define BASE_LCD_CLKSEL_32KHZOSC (0 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_LCD_CLKSEL_IRC (1 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_LCD_CLKSEL_ENET_RXCLK (2 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_LCD_CLKSEL_ENET_TXCLK (3 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_LCD_CLKSEL_GPCLKIN (4 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_LCD_CLKSEL_XTAL (6 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_LCD_CLKSEL_PLL0AUDIO (8 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_LCD_CLKSEL_PLL1 (9 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_LCD_CLKSEL_IDIVA (12 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_LCD_CLKSEL_IDIVB (13 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_LCD_CLKSEL_IDIVC (14 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_LCD_CLKSEL_IDIVD (15 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_LCD_CLKSEL_IDIVE (16 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVE */ +#define BASE_LCD_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_LCD_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_LCD_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_LCD_CLK_CLKSEL_MASK (31 << BASE_LCD_CLK_CLKSEL_SHIFT) +# define BASE_LCD_CLKSEL_32KHZOSC (0 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_LCD_CLKSEL_IRC (1 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_LCD_CLKSEL_ENET_RXCLK (2 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_LCD_CLKSEL_ENET_TXCLK (3 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_LCD_CLKSEL_GPCLKIN (4 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_LCD_CLKSEL_XTAL (6 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_LCD_CLKSEL_PLL0AUDIO (8 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_LCD_CLKSEL_PLL1 (9 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_LCD_CLKSEL_IDIVA (12 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_LCD_CLKSEL_IDIVB (13 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_LCD_CLKSEL_IDIVC (14 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_LCD_CLKSEL_IDIVD (15 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_LCD_CLKSEL_IDIVE (16 << BASE_LCD_CTRL_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 12 control register (BASE_VADC_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_VADC_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_VADC_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_VADC_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_VADC_CLK_CLKSEL_MASK (31 << BASE_VADC_CLK_CLKSEL_SHIFT) -# define BASE_VADC_CLKSEL_32KHZOSC (0 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_VADC_CLKSEL_IRC (1 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_VADC_CLKSEL_ENET_RXCLK (2 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_VADC_CLKSEL_ENET_TXCLK (3 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_VADC_CLKSEL_GPCLKIN (4 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_VADC_CLKSEL_XTAL (6 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_VADC_CLKSEL_PLL0AUDIO (8 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_VADC_CLKSEL_PLL1 (9 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_VADC_CLKSEL_IDIVA (12 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_VADC_CLKSEL_IDIVB (13 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_VADC_CLKSEL_IDIVC (14 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_VADC_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_VADC_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_VADC_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_VADC_CLK_CLKSEL_MASK (31 << BASE_VADC_CLK_CLKSEL_SHIFT) +# define BASE_VADC_CLKSEL_32KHZOSC (0 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_VADC_CLKSEL_IRC (1 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_VADC_CLKSEL_ENET_RXCLK (2 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_VADC_CLKSEL_ENET_TXCLK (3 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_VADC_CLKSEL_GPCLKIN (4 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_VADC_CLKSEL_XTAL (6 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_VADC_CLKSEL_PLL0AUDIO (8 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_VADC_CLKSEL_PLL1 (9 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_VADC_CLKSEL_IDIVA (12 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_VADC_CLKSEL_IDIVB (13 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_VADC_CLKSEL_IDIVC (14 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_VADC_CLKSEL_IDIVD (15 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_VADC_CLKSEL_IDIVE (16 << BASE_VADC_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 14 control register (BASE_SSP0_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_SSP0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_SSP0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_SSP0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_SSP0_CLK_CLKSEL_MASK (31 << BASE_SSP0_CLK_CLKSEL_SHIFT) -# define BASE_SSP0_CLKSEL_32KHZOSC (0 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SSP0_CLKSEL_IRC (1 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SSP0_CLKSEL_ENET_RXCLK (2 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SSP0_CLKSEL_ENET_TXCLK (3 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SSP0_CLKSEL_GPCLKIN (4 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SSP0_CLKSEL_XTAL (6 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SSP0_CLKSEL_PLL0AUDIO (8 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SSP0_CLKSEL_PLL1 (9 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SSP0_CLKSEL_IDIVA (12 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SSP0_CLKSEL_IDIVB (13 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SSP0_CLKSEL_IDIVC (14 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SSP0_CLKSEL_IDIVD (15 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SSP0_CLKSEL_IDIVE (16 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_SSP0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_SSP0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_SSP0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_SSP0_CLK_CLKSEL_MASK (31 << BASE_SSP0_CLK_CLKSEL_SHIFT) +# define BASE_SSP0_CLKSEL_32KHZOSC (0 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SSP0_CLKSEL_IRC (1 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SSP0_CLKSEL_ENET_RXCLK (2 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SSP0_CLKSEL_ENET_TXCLK (3 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SSP0_CLKSEL_GPCLKIN (4 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SSP0_CLKSEL_XTAL (6 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SSP0_CLKSEL_PLL0AUDIO (8 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SSP0_CLKSEL_PLL1 (9 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SSP0_CLKSEL_IDIVA (12 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SSP0_CLKSEL_IDIVB (13 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SSP0_CLKSEL_IDIVC (14 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SSP0_CLKSEL_IDIVD (15 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SSP0_CLKSEL_IDIVE (16 << BASE_SSP0_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 15 control register (BASE_SSP1_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_SSP1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_SSP1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_SSP1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_SSP1_CLK_CLKSEL_MASK (31 << BASE_SSP1_CLK_CLKSEL_SHIFT) -# define BASE_SSP1_CLKSEL_32KHZOSC (0 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_SSP1_CLKSEL_IRC (1 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_SSP1_CLKSEL_ENET_RXCLK (2 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_SSP1_CLKSEL_ENET_TXCLK (3 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_SSP1_CLKSEL_GPCLKIN (4 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_SSP1_CLKSEL_XTAL (6 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_SSP1_CLKSEL_PLL0AUDIO (8 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_SSP1_CLKSEL_PLL1 (9 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_SSP1_CLKSEL_IDIVA (12 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_SSP1_CLKSEL_IDIVB (13 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_SSP1_CLKSEL_IDIVC (14 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_SSP1_CLKSEL_IDIVD (15 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_SSP1_CLKSEL_IDIVE (16 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVE */ +#define BASE_SSP1_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_SSP1_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_SSP1_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_SSP1_CLK_CLKSEL_MASK (31 << BASE_SSP1_CLK_CLKSEL_SHIFT) +# define BASE_SSP1_CLKSEL_32KHZOSC (0 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_SSP1_CLKSEL_IRC (1 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_SSP1_CLKSEL_ENET_RXCLK (2 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_SSP1_CLKSEL_ENET_TXCLK (3 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_SSP1_CLKSEL_GPCLKIN (4 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_SSP1_CLKSEL_XTAL (6 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_SSP1_CLKSEL_PLL0AUDIO (8 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_SSP1_CLKSEL_PLL1 (9 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_SSP1_CLKSEL_IDIVA (12 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_SSP1_CLKSEL_IDIVB (13 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_SSP1_CLKSEL_IDIVC (14 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_SSP1_CLKSEL_IDIVD (15 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_SSP1_CLKSEL_IDIVE (16 << BASE_SSP1_CTRL_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ -/* Output stage 16 control register (BASE_UART0_CLK) */ +/* Output stage 16 control register (BASE_USART0_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_UART0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_UART0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ +#define BASE_USART0_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_USART0_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ /* Bits 12-23: Reserved */ -#define BASE_UART0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_UART0_CLK_CLKSEL_MASK (31 << BASE_UART0_CLK_CLKSEL_SHIFT) -# define BASE_UART0_CLKSEL_32KHZOSC (0 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_UART0_CLKSEL_IRC (1 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_UART0_CLKSEL_ENET_RXCLK (2 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_UART0_CLKSEL_ENET_TXCLK (3 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_UART0_CLKSEL_GPCLKIN (4 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_UART0_CLKSEL_XTAL (6 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_UART0_CLKSEL_PLL0AUDIO (8 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_UART0_CLKSEL_PLL1 (9 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_UART0_CLKSEL_IDIVA (12 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_UART0_CLKSEL_IDIVB (13 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_UART0_CLKSEL_IDIVC (14 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_UART0_CLKSEL_IDIVD (15 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_UART0_CLKSEL_IDIVE (16 << BASE_UART0_CTRL_CLKSEL_SHIFT) /* IDIVE */ +#define BASE_USART0_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_USART0_CLK_CLKSEL_MASK (31 << BASE_USART0_CLK_CLKSEL_SHIFT) +# define BASE_USART0_CLKSEL_32KHZOSC (0 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USART0_CLKSEL_IRC (1 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USART0_CLKSEL_ENET_RXCLK (2 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USART0_CLKSEL_ENET_TXCLK (3 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USART0_CLKSEL_GPCLKIN (4 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USART0_CLKSEL_XTAL (6 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USART0_CLKSEL_PLL0AUDIO (8 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USART0_CLKSEL_PLL1 (9 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USART0_CLKSEL_IDIVA (12 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USART0_CLKSEL_IDIVB (13 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USART0_CLKSEL_IDIVC (14 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USART0_CLKSEL_IDIVD (15 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USART0_CLKSEL_IDIVE (16 << BASE_USART0_CTRL_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ -/* Output stage 18 control register (BASE_UART2_CLK) */ +/* Output stage 18 control register (BASE_USART2_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_UART2_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ +#define BASE_USART2_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ /* Bits 1-10: Reserved */ -#define BASE_UART2_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ +#define BASE_USART2_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ /* Bits 12-23: Reserved */ -#define BASE_UART2_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_UART2_CLK_CLKSEL_MASK (31 << BASE_UART2_CLK_CLKSEL_SHIFT) -# define BASE_UART2_CLKSEL_32KHZOSC (0 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_UART2_CLKSEL_IRC (1 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_UART2_CLKSEL_ENET_RXCLK (2 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_UART2_CLKSEL_ENET_TXCLK (3 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_UART2_CLKSEL_GPCLKIN (4 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_UART2_CLKSEL_XTAL (6 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_UART2_CLKSEL_PLL0AUDIO (8 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_UART2_CLKSEL_PLL1 (9 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_UART2_CLKSEL_IDIVA (12 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_UART2_CLKSEL_IDIVB (13 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_UART2_CLKSEL_IDIVC (14 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_UART2_CLKSEL_IDIVD (15 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_UART2_CLKSEL_IDIVE (16 << BASE_UART2_CTRL_CLKSEL_SHIFT) /* IDIVE */ +#define BASE_USART2_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_USART2_CLK_CLKSEL_MASK (31 << BASE_USART2_CLK_CLKSEL_SHIFT) +# define BASE_USART2_CLKSEL_32KHZOSC (0 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USART2_CLKSEL_IRC (1 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USART2_CLKSEL_ENET_RXCLK (2 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USART2_CLKSEL_ENET_TXCLK (3 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USART2_CLKSEL_GPCLKIN (4 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USART2_CLKSEL_XTAL (6 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USART2_CLKSEL_PLL0AUDIO (8 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USART2_CLKSEL_PLL1 (9 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USART2_CLKSEL_IDIVA (12 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USART2_CLKSEL_IDIVB (13 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USART2_CLKSEL_IDIVC (14 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USART2_CLKSEL_IDIVD (15 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USART2_CLKSEL_IDIVE (16 << BASE_USART2_CTRL_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ -/* Output stage 19 control register (BASE_UART3_CLK) */ +/* Output stage 19 control register (BASE_USART3_CLK) */ /* NOTE: Clocks 4-19 are identical */ -#define BASE_UART3_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ +#define BASE_USART3_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ /* Bits 1-10: Reserved */ -#define BASE_UART3_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ +#define BASE_USART3_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ /* Bits 12-23: Reserved */ -#define BASE_UART3_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_UART3_CLK_CLKSEL_MASK (31 << BASE_UART3_CLK_CLKSEL_SHIFT) -# define BASE_UART3_CLKSEL_32KHZOSC (0 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_UART3_CLKSEL_IRC (1 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_UART3_CLKSEL_ENET_RXCLK (2 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_UART3_CLKSEL_ENET_TXCLK (3 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_UART3_CLKSEL_GPCLKIN (4 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_UART3_CLKSEL_XTAL (6 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_UART3_CLKSEL_PLL0AUDIO (8 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_UART3_CLKSEL_PLL1 (9 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_UART3_CLKSEL_IDIVA (12 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_UART3_CLKSEL_IDIVB (13 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_UART3_CLKSEL_IDIVC (14 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_UART3_CLKSEL_IDIVD (15 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_UART3_CLKSEL_IDIVE (16 << BASE_UART3_CTRL_CLKSEL_SHIFT) /* IDIVE */ +#define BASE_USART3_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_USART3_CLK_CLKSEL_MASK (31 << BASE_USART3_CLK_CLKSEL_SHIFT) +# define BASE_USART3_CLKSEL_32KHZOSC (0 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_USART3_CLKSEL_IRC (1 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_USART3_CLKSEL_ENET_RXCLK (2 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_USART3_CLKSEL_ENET_TXCLK (3 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_USART3_CLKSEL_GPCLKIN (4 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_USART3_CLKSEL_XTAL (6 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_USART3_CLKSEL_PLL0AUDIO (8 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_USART3_CLKSEL_PLL1 (9 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_USART3_CLKSEL_IDIVA (12 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_USART3_CLKSEL_IDIVB (13 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_USART3_CLKSEL_IDIVC (14 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_USART3_CLKSEL_IDIVD (15 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_USART3_CLKSEL_IDIVE (16 << BASE_USART3_CTRL_CLKSEL_SHIFT) /* IDIVE */ /* Bits 29-31: Reserved */ /* Output stage 20 control register (BASE_OUT_CLK) */ -#define BASE_OUT_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_OUT_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_OUT_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_OUT_CLK_CLKSEL_MASK (31 << BASE_OUT_CLK_CLKSEL_SHIFT) -# define BASE_OUT_CLKSEL_32KHZOSC (0 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_OUT_CLKSEL_IRC (1 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_OUT_CLKSEL_ENET_RXCLK (2 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_OUT_CLKSEL_ENET_TXCLK (3 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_OUT_CLKSEL_GPCLKIN (4 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_OUT_CLKSEL_XTAL (6 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_OUT_CLKSEL_PLL0USB (7 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define BASE_OUT_CLKSEL_PLL0AUDIO (8 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_OUT_CLKSEL_PLL1 (9 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_OUT_CLKSEL_IDIVA (12 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_OUT_CLKSEL_IDIVB (13 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_OUT_CLKSEL_IDIVC (14 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_OUT_CLKSEL_IDIVD (15 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_OUT_CLKSEL_IDIVE (16 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_OUT_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_OUT_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_OUT_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_OUT_CLK_CLKSEL_MASK (31 << BASE_OUT_CLK_CLKSEL_SHIFT) +# define BASE_OUT_CLKSEL_32KHZOSC (0 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_OUT_CLKSEL_IRC (1 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_OUT_CLKSEL_ENET_RXCLK (2 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_OUT_CLKSEL_ENET_TXCLK (3 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_OUT_CLKSEL_GPCLKIN (4 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_OUT_CLKSEL_XTAL (6 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_OUT_CLKSEL_PLL0USB (7 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0USB */ +# define BASE_OUT_CLKSEL_PLL0AUDIO (8 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_OUT_CLKSEL_PLL1 (9 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_OUT_CLKSEL_IDIVA (12 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_OUT_CLKSEL_IDIVB (13 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_OUT_CLKSEL_IDIVC (14 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_OUT_CLKSEL_IDIVD (15 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_OUT_CLKSEL_IDIVE (16 << BASE_OUT_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 25 control register (BASE_APLL_CLK) */ -#define BASE_APLL_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_APLL_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_APLL_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_APLL_CLK_CLKSEL_MASK (31 << BASE_APLL_CLK_CLKSEL_SHIFT) -# define BASE_APLL_CLKSEL_32KHZOSC (0 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_APLL_CLKSEL_IRC (1 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_APLL_CLKSEL_ENET_RXCLK (2 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_APLL_CLKSEL_ENET_TXCLK (3 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_APLL_CLKSEL_GPCLKIN (4 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_APLL_CLKSEL_XTAL (6 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_APLL_CLKSEL_PLL0AUDIO (8 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_APLL_CLKSEL_PLL1 (9 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_APLL_CLKSEL_IDIVA (12 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_APLL_CLKSEL_IDIVB (13 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_APLL_CLKSEL_IDIVC (14 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_APLL_CLKSEL_IDIVD (15 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_APLL_CLKSEL_IDIVE (16 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_APLL_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_APLL_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_APLL_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_APLL_CLK_CLKSEL_MASK (31 << BASE_APLL_CLK_CLKSEL_SHIFT) +# define BASE_APLL_CLKSEL_32KHZOSC (0 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_APLL_CLKSEL_IRC (1 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_APLL_CLKSEL_ENET_RXCLK (2 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_APLL_CLKSEL_ENET_TXCLK (3 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_APLL_CLKSEL_GPCLKIN (4 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_APLL_CLKSEL_XTAL (6 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_APLL_CLKSEL_PLL0AUDIO (8 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_APLL_CLKSEL_PLL1 (9 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_APLL_CLKSEL_IDIVA (12 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_APLL_CLKSEL_IDIVB (13 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_APLL_CLKSEL_IDIVC (14 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_APLL_CLKSEL_IDIVD (15 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_APLL_CLKSEL_IDIVE (16 << BASE_APLL_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /* Output stage 26/27 control register (BASE_CGU_OUT0/1_CLK) */ /* NOTE: Clocks 26-27 are identical */ -#define BASE_CGU_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ - /* Bits 1-10: Reserved */ -#define BASE_CGU_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ - /* Bits 12-23: Reserved */ -#define BASE_CGU_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ -#define BASE_CGU_CLK_CLKSEL_MASK (31 << BASE_CGU_CLK_CLKSEL_SHIFT) -# define BASE_CGU_CLKSEL_32KHZOSC (0 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ -# define BASE_CGU_CLKSEL_IRC (1 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IRC (default) */ -# define BASE_CGU_CLKSEL_ENET_RXCLK (2 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ -# define BASE_CGU_CLKSEL_ENET_TXCLK (3 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ -# define BASE_CGU_CLKSEL_GPCLKIN (4 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ -# define BASE_CGU_CLKSEL_XTAL (6 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ -# define BASE_CGU_CLKSEL_PLL0USB (7 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0USB */ -# define BASE_CGU_CLKSEL_PLL0AUDIO (8 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ -# define BASE_CGU_CLKSEL_PLL1 (9 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL1 */ -# define BASE_CGU_CLKSEL_IDIVA (12 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVA */ -# define BASE_CGU_CLKSEL_IDIVB (13 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVB */ -# define BASE_CGU_CLKSEL_IDIVC (14 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVC */ -# define BASE_CGU_CLKSEL_IDIVD (15 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVD */ -# define BASE_CGU_CLKSEL_IDIVE (16 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVE */ - /* Bits 29-31: Reserved */ +#define BASE_CGU_CLK_PD (1 << 0) /* Bit 0: Output stage power down */ + /* Bits 1-10: Reserved */ +#define BASE_CGU_CLK_AUTOBLOCK (1 << 11) /* Bit 11: Block clock during frequency change */ + /* Bits 12-23: Reserved */ +#define BASE_CGU_CLK_CLKSEL_SHIFT (24) /* Bits 24-28: Clock source selection */ +#define BASE_CGU_CLK_CLKSEL_MASK (31 << BASE_CGU_CLK_CLKSEL_SHIFT) +# define BASE_CGU_CLKSEL_32KHZOSC (0 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* 32 kHz oscillator */ +# define BASE_CGU_CLKSEL_IRC (1 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IRC (default) */ +# define BASE_CGU_CLKSEL_ENET_RXCLK (2 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_RX_CLK */ +# define BASE_CGU_CLKSEL_ENET_TXCLK (3 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* ENET_TX_CLK */ +# define BASE_CGU_CLKSEL_GPCLKIN (4 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* GP_CLKIN */ +# define BASE_CGU_CLKSEL_XTAL (6 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* Crystal oscillator */ +# define BASE_CGU_CLKSEL_PLL0USB (7 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0USB */ +# define BASE_CGU_CLKSEL_PLL0AUDIO (8 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL0AUDIO */ +# define BASE_CGU_CLKSEL_PLL1 (9 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* PLL1 */ +# define BASE_CGU_CLKSEL_IDIVA (12 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVA */ +# define BASE_CGU_CLKSEL_IDIVB (13 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVB */ +# define BASE_CGU_CLKSEL_IDIVC (14 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVC */ +# define BASE_CGU_CLKSEL_IDIVD (15 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVD */ +# define BASE_CGU_CLKSEL_IDIVE (16 << BASE_CGU_CTRL_CLKSEL_SHIFT) /* IDIVE */ + /* Bits 29-31: Reserved */ /**************************************************************************************************** * Public Types diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h index 641fcf8c65..993242ebe4 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gima.h @@ -49,7 +49,7 @@ /* Timer capture input multiplexor registers */ -#define LPC32_GIMA_CAP_OFFSET(t,i) (((t) << 4) | ((i) << 2)) +#define LPC43_GIMA_CAP_OFFSET(t,i) (((t) << 4) | ((i) << 2)) #define LPC43_GIMA_CAP00_OFFSET 0x0000 /* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ #define LPC43_GIMA_CAP01_OFFSET 0x0004 /* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ #define LPC43_GIMA_CAP02_OFFSET 0x0008 /* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ @@ -67,7 +67,7 @@ #define LPC43_GIMA_CAP32_OFFSET 0x0038 /* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ #define LPC43_GIMA_CAP33_OFFSET 0x003c /* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ -#define LPC32_GIMA_CTIN_OFFSET(i) (0x0040 + ((i) << 2)) +#define LPC43_GIMA_CTIN_OFFSET(i) (0x0040 + ((i) << 2)) #define LPC43_GIMA_CTIN0_OFFSET 0x0040 /* SCT CTIN_0 capture input multiplexer (GIMA output 16) */ #define LPC43_GIMA_CTIN1_OFFSET 0x0044 /* SCT CTIN_1 capture input multiplexer (GIMA output 17) */ #define LPC43_GIMA_CTIN2_OFFSET 0x0048 /* SCT CTIN_2 capture input multiplexer (GIMA output 18) */ @@ -86,7 +86,7 @@ /* Register Addresses *******************************************************************************/ -#define LPC32_GIMA_CAP(t,i) (LPC43_GIMA_BASE+LPC32_GIMA_CAP_OFFSET(t,i)) +#define LPC43_GIMA_CAP(t,i) (LPC43_GIMA_BASE+LPC43_GIMA_CAP_OFFSET(t,i)) #define LPC43_GIMA_CAP00 (LPC43_GIMA_BASE+LPC43_GIMA_CAP00_OFFSET) #define LPC43_GIMA_CAP01 (LPC43_GIMA_BASE+LPC43_GIMA_CAP01_OFFSET) #define LPC43_GIMA_CAP02 (LPC43_GIMA_BASE+LPC43_GIMA_CAP02_OFFSET) @@ -104,7 +104,7 @@ #define LPC43_GIMA_CAP32 (LPC43_GIMA_BASE+LPC43_GIMA_CAP32_OFFSET) #define LPC43_GIMA_CAP33 (LPC43_GIMA_BASE+LPC43_GIMA_CAP33_OFFSET) -#define LPC32_GIMA_CTIN(i) (LPC43_GIMA_BASE+LPC32_GIMA_CTIN_OFFSET(i)) +#define LPC43_GIMA_CTIN(i) (LPC43_GIMA_BASE+LPC43_GIMA_CTIN_OFFSET(i)) #define LPC43_GIMA_CTIN0 (LPC43_GIMA_BASE+LPC43_GIMA_CTIN0_OFFSET) #define LPC43_GIMA_CTIN1 (LPC43_GIMA_BASE+LPC43_GIMA_CTIN1_OFFSET) #define LPC43_GIMA_CTIN2 (LPC43_GIMA_BASE+LPC43_GIMA_CTIN2_OFFSET) diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h index e4cf3276b5..f885c1387e 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_gpdma.h @@ -349,11 +349,11 @@ # define GPDMA_CONFIG_SRCPER_SSP1RX_2 (6 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP1 receive */ # define GPDMA_CONFIG_SRCPER_SGPIO14_2 (6 << GPDMA_CONFIG_SRCPER_SHIFT) /* SGPIO14 */ # define GPDMA_CONFIG_SRCPER_T3MAT0_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* Timer3 match 0 */ -# define GPDMA_CONFIG_SRCPER_U3TX_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* UART3 transmit */ +# define GPDMA_CONFIG_SRCPER_U3TX_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART3 transmit */ # define GPDMA_CONFIG_SRCPER_SCTD0_1 (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* SCT DMA request 0 */ # define GPDMA_CONFIG_SRCPER_VADCWR (7 << GPDMA_CONFIG_SRCPER_SHIFT) /* VADC write */ # define GPDMA_CONFIG_SRCPER_T3MAT1_2 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* Timer3 match 1 */ -# define GPDMA_CONFIG_SRCPER_U3RX_1 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* UART3 receive */ +# define GPDMA_CONFIG_SRCPER_U3RX_1 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* USART3 receive */ # define GPDMA_CONFIG_SRCPER_SCTD1_1 (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* SCT DMA request 1 */ # define GPDMA_CONFIG_SRCPER_VADCRD (8 << GPDMA_CONFIG_SRCPER_SHIFT) /* VADC read */ # define GPDMA_CONFIG_SRCPER_SSP0RX (9 << GPDMA_CONFIG_SRCPER_SHIFT) /* SSP0 receive */ @@ -405,11 +405,11 @@ # define GPDMA_CONFIG_DESTPER_SSP1RX_2 (6 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP1 receive */ # define GPDMA_CONFIG_DESTPER_SGPIO14_2 (6 << GPDMA_CONFIG_DESTPER_SHIFT) /* SGPIO14 */ # define GPDMA_CONFIG_DESTPER_T3MAT0_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* Timer3 match 0 */ -# define GPDMA_CONFIG_DESTPER_U3TX_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* UART3 transmit */ +# define GPDMA_CONFIG_DESTPER_U3TX_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART3 transmit */ # define GPDMA_CONFIG_DESTPER_SCTD0_1 (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* SCT DMA request 0 */ # define GPDMA_CONFIG_DESTPER_VADCWR (7 << GPDMA_CONFIG_DESTPER_SHIFT) /* VADC write */ # define GPDMA_CONFIG_DESTPER_T3MAT1_2 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* Timer3 match 1 */ -# define GPDMA_CONFIG_DESTPER_U3RX_1 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* UART3 receive */ +# define GPDMA_CONFIG_DESTPER_U3RX_1 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* USART3 receive */ # define GPDMA_CONFIG_DESTPER_SCTD1_1 (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* SCT DMA request 1 */ # define GPDMA_CONFIG_DESTPER_VADCRD (8 << GPDMA_CONFIG_DESTPER_SHIFT) /* VADC read */ # define GPDMA_CONFIG_DESTPER_SSP0RX (9 << GPDMA_CONFIG_DESTPER_SHIFT) /* SSP0 receive */ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h index 5b4ac6c7ca..67b5af319b 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_otp.h @@ -47,88 +47,88 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ -#define LPC43_OTP_MEM00_OFFSET 0x0010 /* General purpose OTP memory 0, word 0 */ -#define LPC43_OTP_MEM01_OFFSET 0x0014 /* General purpose OTP memory 0, word 1 */ -#define LPC43_OTP_MEM02_OFFSET 0x0018 /* General purpose OTP memory 0, word 2 */ -#define LPC43_OTP_MEM03_OFFSET 0x001c /* General purpose OTP memory 0, word 3 */ +#define LPC43_OTP_MEM00_OFFSET 0x0010 /* General purpose OTP memory 0, word 0 */ +#define LPC43_OTP_MEM01_OFFSET 0x0014 /* General purpose OTP memory 0, word 1 */ +#define LPC43_OTP_MEM02_OFFSET 0x0018 /* General purpose OTP memory 0, word 2 */ +#define LPC43_OTP_MEM03_OFFSET 0x001c /* General purpose OTP memory 0, word 3 */ -#define LPC43_OTP_MEM10_OFFSET 0x0020 /* General purpose OTP memory 1, word 0 */ -#define LPC43_OTP_MEM11_OFFSET 0x0024 /* General purpose OTP memory 1, word 1 */ -#define LPC43_OTP_MEM12_OFFSET 0x0028 /* General purpose OTP memory 1, word 2 */ -#define LPC43_OTP_MEM13_OFFSET 0x002c /* General purpose OTP memory 1, word 3 */ +#define LPC43_OTP_MEM10_OFFSET 0x0020 /* General purpose OTP memory 1, word 0 */ +#define LPC43_OTP_MEM11_OFFSET 0x0024 /* General purpose OTP memory 1, word 1 */ +#define LPC43_OTP_MEM12_OFFSET 0x0028 /* General purpose OTP memory 1, word 2 */ +#define LPC43_OTP_MEM13_OFFSET 0x002c /* General purpose OTP memory 1, word 3 */ -#define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */ -#define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */ -#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */ +#define LPC43_OTP_MEM20_OFFSET 0x0034 /* General purpose OTP memory 2, word 0 */ +#define LPC43_OTP_MEM21_OFFSET 0x0038 /* General purpose OTP memory 2, word 1 */ +#define LPC43_OTP_MEM22_OFFSET 0x003c /* General purpose OTP memory 2, word 2 */ -#define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */ -#define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */ -#define LPC43_OTP_AES02_OFFSET 0x0018 /* AES key 0, word 2 */ -#define LPC43_OTP_AES03_OFFSET 0x001c /* AES key 0, word 3 */ +#define LPC43_OTP_AES00_OFFSET 0x0010 /* AES key 0, word 0 */ +#define LPC43_OTP_AES01_OFFSET 0x0014 /* AES key 0, word 1 */ +#define LPC43_OTP_AES02_OFFSET 0x0018 /* AES key 0, word 2 */ +#define LPC43_OTP_AES03_OFFSET 0x001c /* AES key 0, word 3 */ -#define LPC43_OTP_AES10_OFFSET 0x0020 /* AES key 1, word 0 */ -#define LPC43_OTP_AES11_OFFSET 0x0024 /* AES key 1, word 1 */ -#define LPC43_OTP_AES12_OFFSET 0x0028 /* AES key 1, word 2 */ -#define LPC43_OTP_AES13_OFFSET 0x002c /* AES key 1, word 3 */ +#define LPC43_OTP_AES10_OFFSET 0x0020 /* AES key 1, word 0 */ +#define LPC43_OTP_AES11_OFFSET 0x0024 /* AES key 1, word 1 */ +#define LPC43_OTP_AES12_OFFSET 0x0028 /* AES key 1, word 2 */ +#define LPC43_OTP_AES13_OFFSET 0x002c /* AES key 1, word 3 */ -#define LPC43_OTP_CCD_OFFSET 0x0030 /* Customer control data */ -#define LPC43_OTP_USBID_OFFSET 0x0034 /* USB ID */ +#define LPC43_OTP_CCD_OFFSET 0x0030 /* Customer control data */ +#define LPC43_OTP_USBID_OFFSET 0x0034 /* USB ID */ /* Register Addresses ***************************************************************/ -#define LPC43_OTP_MEM00 (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET) -#define LPC43_OTP_MEM01 (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET) -#define LPC43_OTP_MEM02 (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET) -#define LPC43_OTP_MEM03 (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET) +#define LPC43_OTP_MEM00 (LPC43_OTPC_BASE+LPC43_OTP_MEM00_OFFSET) +#define LPC43_OTP_MEM01 (LPC43_OTPC_BASE+LPC43_OTP_MEM01_OFFSET) +#define LPC43_OTP_MEM02 (LPC43_OTPC_BASE+LPC43_OTP_MEM02_OFFSET) +#define LPC43_OTP_MEM03 (LPC43_OTPC_BASE+LPC43_OTP_MEM03_OFFSET) -#define LPC43_OTP_MEM10 (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET) -#define LPC43_OTP_MEM11 (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET) -#define LPC43_OTP_MEM12 (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET) -#define LPC43_OTP_MEM13 (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET) +#define LPC43_OTP_MEM10 (LPC43_OTPC_BASE+LPC43_OTP_MEM10_OFFSET) +#define LPC43_OTP_MEM11 (LPC43_OTPC_BASE+LPC43_OTP_MEM11_OFFSET) +#define LPC43_OTP_MEM12 (LPC43_OTPC_BASE+LPC43_OTP_MEM12_OFFSET) +#define LPC43_OTP_MEM13 (LPC43_OTPC_BASE+LPC43_OTP_MEM13_OFFSET) -#define LPC43_OTP_MEM20 (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET) -#define LPC43_OTP_MEM21 (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET) -#define LPC43_OTP_MEM22 (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET) +#define LPC43_OTP_MEM20 (LPC43_OTPC_BASE+LPC43_OTP_MEM20_OFFSET) +#define LPC43_OTP_MEM21 (LPC43_OTPC_BASE+LPC43_OTP_MEM21_OFFSET) +#define LPC43_OTP_MEM22 (LPC43_OTPC_BASE+LPC43_OTP_MEM22_OFFSET) -#define LPC43_OTP_AES00 (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET) -#define LPC43_OTP_AES01 (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET) -#define LPC43_OTP_AES02 (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET) -#define LPC43_OTP_AES03 (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET) +#define LPC43_OTP_AES00 (LPC43_OTPC_BASE+LPC43_OTP_AES00_OFFSET) +#define LPC43_OTP_AES01 (LPC43_OTPC_BASE+LPC43_OTP_AES01_OFFSET) +#define LPC43_OTP_AES02 (LPC43_OTPC_BASE+LPC43_OTP_AES02_OFFSET) +#define LPC43_OTP_AES03 (LPC43_OTPC_BASE+LPC43_OTP_AES03_OFFSET) -#define LPC43_OTP_AES10 (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET) -#define LPC43_OTP_AES11 (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET) -#define LPC43_OTP_AES12 (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET) -#define LPC43_OTP_AES13 (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET) +#define LPC43_OTP_AES10 (LPC43_OTPC_BASE+LPC43_OTP_AES10_OFFSET) +#define LPC43_OTP_AES11 (LPC43_OTPC_BASE+LPC43_OTP_AES11_OFFSET) +#define LPC43_OTP_AES12 (LPC43_OTPC_BASE+LPC43_OTP_AES12_OFFSET) +#define LPC43_OTP_AES13 (LPC43_OTPC_BASE+LPC43_OTP_AES13_OFFSET) -#define LPC43_OTP_CCD (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET) -#define LPC43_OTP_USBID (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET) +#define LPC43_OTP_CCD (LPC43_OTPC_BASE+LPC43_OTP_CCD_OFFSET) +#define LPC43_OTP_USBID (LPC43_OTPC_BASE+LPC43_OTP_USBID_OFFSET) /* Register Bit Definitions *********************************************************/ /* Customer control data */ - /* Bits 0-22: Reserved */ -#define OTP_CCD_USBID (1 << 23) /* Bit 23: USB ID enable */ - /* Bit 24: Reserved */ -#define OPT_CCD_BOOTSRC_SHIFT (25) /* Bits 25-28: Boot source selection in OTP */ -#define OPT_CCD_BOOTSRC_MASK (15 << OPT_CCD_BOOTSRC_SHIFT) -# define OPT_CCD_BOOTSRC_EXT (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */ -# define OPT_CCD_BOOTSRC_UART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* UART0 */ -# define OPT_CCD_BOOTSRC_EMC8 (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */ -# define OPT_CCD_BOOTSRC_EMC16 (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */ -# define OPT_CCD_BOOTSRC_EMC32 (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */ -# define OPT_CCD_BOOTSRC_USB0 (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */ -# define OPT_CCD_BOOTSRC_USB1 (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */ -# define OPT_CCD_BOOTSRC_SPI (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */ -# define OPT_CCD_BOOTSRC_UART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* UART3 */ - /* Bits 29-30: Reserved */ -#define OTP_CCD_JTAGDIS (1 << 31) /* Bit 31: JTAG disable */ + /* Bits 0-22: Reserved */ +#define OTP_CCD_USBID (1 << 23) /* Bit 23: USB ID enable */ + /* Bit 24: Reserved */ +#define OPT_CCD_BOOTSRC_SHIFT (25) /* Bits 25-28: Boot source selection in OTP */ +#define OPT_CCD_BOOTSRC_MASK (15 << OPT_CCD_BOOTSRC_SHIFT) +# define OPT_CCD_BOOTSRC_EXT (0 << OPT_CCD_BOOTSRC_SHIFT) /* External pins */ +# define OPT_CCD_BOOTSRC_USART0 (1 << OPT_CCD_BOOTSRC_SHIFT) /* USART0 */ +# define OPT_CCD_BOOTSRC_EMC8 (3 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 8-bit */ +# define OPT_CCD_BOOTSRC_EMC16 (4 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 16-bit */ +# define OPT_CCD_BOOTSRC_EMC32 (5 << OPT_CCD_BOOTSRC_SHIFT) /* EMC 32-bit */ +# define OPT_CCD_BOOTSRC_USB0 (6 << OPT_CCD_BOOTSRC_SHIFT) /* USB0 */ +# define OPT_CCD_BOOTSRC_USB1 (7 << OPT_CCD_BOOTSRC_SHIFT) /* USB1 */ +# define OPT_CCD_BOOTSRC_SPI (8 << OPT_CCD_BOOTSRC_SHIFT) /* SPI (via SSP) */ +# define OPT_CCD_BOOTSRC_USART3 (9 << OPT_CCD_BOOTSRC_SHIFT) /* USART3 */ + /* Bits 29-30: Reserved */ +#define OTP_CCD_JTAGDIS (1 << 31) /* Bit 31: JTAG disable */ /* USB ID */ -#define OTP_USBID_VID_SHIFT (0) /* Bits 0-15: USB vendor ID */ -#define OTP_USBID_VID_MASK (0xffff << OTP_USBID_VID_SHIFT) -#define OTP_USBID_PID_SHIFT (0) /* Bits 16-31: USB product ID */ -#define OTP_USBID_PID_MASK (0xffff << OTP_USBID_PID_SHIFT) +#define OTP_USBID_VID_SHIFT (0) /* Bits 0-15: USB vendor ID */ +#define OTP_USBID_VID_MASK (0xffff << OTP_USBID_VID_SHIFT) +#define OTP_USBID_PID_SHIFT (0) /* Bits 16-31: USB product ID */ +#define OTP_USBID_PID_MASK (0xffff << OTP_USBID_PID_SHIFT) /* OTP API *************************************************************************/ /* The AES is controlled through a set of simple API calls located in the LPC43xx diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h index 8b41a0072d..511c515a28 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_pmc.h @@ -47,13 +47,13 @@ ************************************************************************************/ /* Register Offsets *****************************************************************/ -#define LPC32_PD0_SLEEP0_HWENA_OFFSET 0x0000 /* Hardware sleep event enable register */ -#define LPC32_PD0_SLEEP0_MODE_OFFSET 0x001c /* Power-down mode control register */ +#define LPC43_PD0_SLEEP0_HWENA_OFFSET 0x0000 /* Hardware sleep event enable register */ +#define LPC43_PD0_SLEEP0_MODE_OFFSET 0x001c /* Power-down mode control register */ /* Register Addresses ***************************************************************/ -#define LPC32_PD0_SLEEP0_HWENA (LPC43_PMC_BASE+LPC32_PD0_SLEEP0_HWENA_OFFSET) -#define LPC32_PD0_SLEEP0_MODE (LPC43_PMC_BASE+LPC32_PD0_SLEEP0_MODE_OFFSET) +#define LPC43_PD0_SLEEP0_HWENA (LPC43_PMC_BASE+LPC43_PD0_SLEEP0_HWENA_OFFSET) +#define LPC43_PD0_SLEEP0_MODE (LPC43_PMC_BASE+LPC43_PD0_SLEEP0_MODE_OFFSET) /* Register Bit Definitions *********************************************************/ diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h index 2c2f997eab..d0338e176f 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_rgu.h @@ -88,10 +88,10 @@ #define RGU_ADC0_RST 40 #define RGU_ADC1_RST 41 #define RGU_DAC_RST 42 -#define RGU_UART0_RST 44 +#define RGU_USART0_RST 44 #define RGU_UART1_RST 45 -#define RGU_UART2_RST 46 -#define RGU_UART3_RST 47 +#define RGU_USART2_RST 46 +#define RGU_USART3_RST 47 #define RGU_I2C0_RST 48 #define RGU_I2C1_RST 49 #define RGU_SSP0_RST 50 @@ -137,10 +137,10 @@ #define LPC43_RGU_EXTSTAT40_OFFSET 0x4a0 /* Reset external status register 40 for ADC0_RST */ #define LPC43_RGU_EXTSTAT41_OFFSET 0x4a4 /* Reset external status register 41 for ADC1_RST */ #define LPC43_RGU_EXTSTAT42_OFFSET 0x4a8 /* Reset external status register 42 for DAC_RST */ -#define LPC43_RGU_EXTSTAT44_OFFSET 0x4b0 /* Reset external status register 44 for UART0_RST */ +#define LPC43_RGU_EXTSTAT44_OFFSET 0x4b0 /* Reset external status register 44 for USART0_RST */ #define LPC43_RGU_EXTSTAT45_OFFSET 0x4b4 /* Reset external status register 45 for UART1_RST */ -#define LPC43_RGU_EXTSTAT46_OFFSET 0x4b8 /* Reset external status register 46 for UART2_RST */ -#define LPC43_RGU_EXTSTAT47_OFFSET 0x4bc /* Reset external status register 47 for UART3_RST */ +#define LPC43_RGU_EXTSTAT46_OFFSET 0x4b8 /* Reset external status register 46 for USART2_RST */ +#define LPC43_RGU_EXTSTAT47_OFFSET 0x4bc /* Reset external status register 47 for USART3_RST */ #define LPC43_RGU_EXTSTAT48_OFFSET 0x4c0 /* Reset external status register 48 for I2C0_RST */ #define LPC43_RGU_EXTSTAT49_OFFSET 0x4c4 /* Reset external status register 49 for I2C1_RST */ #define LPC43_RGU_EXTSTAT50_OFFSET 0x4c8 /* Reset external status register 50 for SSP0_RST */ @@ -245,10 +245,10 @@ #define LPC43_RGU_EXTSTAT_ADC0_RST LPC43_RGU_EXTSTAT40 #define LPC43_RGU_EXTSTAT_ADC1_RST LPC43_RGU_EXTSTAT41 #define LPC43_RGU_EXTSTAT_DAC_RST LPC43_RGU_EXTSTAT42 -#define LPC43_RGU_EXTSTAT_UART0_RST LPC43_RGU_EXTSTAT44 +#define LPC43_RGU_EXTSTAT_USART0_RST LPC43_RGU_EXTSTAT44 #define LPC43_RGU_EXTSTAT_UART1_RST LPC43_RGU_EXTSTAT45 -#define LPC43_RGU_EXTSTAT_UART2_RST LPC43_RGU_EXTSTAT46 -#define LPC43_RGU_EXTSTAT_UART3_RST LPC43_RGU_EXTSTAT47 +#define LPC43_RGU_EXTSTAT_USART2_RST LPC43_RGU_EXTSTAT46 +#define LPC43_RGU_EXTSTAT_USART3_RST LPC43_RGU_EXTSTAT47 #define LPC43_RGU_EXTSTAT_I2C0_RST LPC43_RGU_EXTSTAT48 #define LPC43_RGU_EXTSTAT_I2C1_RST LPC43_RGU_EXTSTAT49 #define LPC43_RGU_EXTSTAT_SSP0_RST LPC43_RGU_EXTSTAT50 @@ -305,10 +305,10 @@ #define RGU_CTRL1_ADC1_RST (1 << 9) #define RGU_CTRL1_DAC_RST (1 << 10) /* Bit 11: Reserved */ -#define RGU_CTRL1_UART0_RST (1 << 12) +#define RGU_CTRL1_USART0_RST (1 << 12) #define RGU_CTRL1_UART1_RST (1 << 13) -#define RGU_CTRL1_UART2_RST (1 << 14) -#define RGU_CTRL1_UART3_RST (1 << 15) +#define RGU_CTRL1_USART2_RST (1 << 14) +#define RGU_CTRL1_USART3_RST (1 << 15) #define RGU_CTRL1_I2C0_RST (1 << 16) #define RGU_CTRL1_I2C1_RST (1 << 17) #define RGU_CTRL1_SSP0_RST (1 << 18) @@ -485,26 +485,26 @@ # define RGU_STATUS2_DAC_RST_HW (1 << RGU_STATUS2_DAC_RST_SHIFT) /* Activated by reset generator */ # define RGU_STATUS2_DAC_RST_SW (3 << RGU_STATUS2_DAC_RST_SHIFT) /* Activated by software */ /* Bits 22-23: Reserved */ -#define RGU_STATUS2_UART0_RST_SHIFT (24) /* Bits 24-24: 25:24 Status of the UART0_RST reset generator output */ -#define RGU_STATUS2_UART0_RST_MASK (3 << RGU_STATUS2_UART0_RST_SHIFT) -# define RGU_STATUS2_UART0_RST_NONE (0 << RGU_STATUS2_UART0_RST_SHIFT) /* No reset activated */ -# define RGU_STATUS2_UART0_RST_HW (1 << RGU_STATUS2_UART0_RST_SHIFT) /* Activated by reset generator */ -# define RGU_STATUS2_UART0_RST_SW (3 << RGU_STATUS2_UART0_RST_SHIFT) /* Activated by software */ +#define RGU_STATUS2_USART0_RST_SHIFT (24) /* Bits 24-24: 25:24 Status of the USART0_RST reset generator output */ +#define RGU_STATUS2_USART0_RST_MASK (3 << RGU_STATUS2_USART0_RST_SHIFT) +# define RGU_STATUS2_USART0_RST_NONE (0 << RGU_STATUS2_USART0_RST_SHIFT) /* No reset activated */ +# define RGU_STATUS2_USART0_RST_HW (1 << RGU_STATUS2_USART0_RST_SHIFT) /* Activated by reset generator */ +# define RGU_STATUS2_USART0_RST_SW (3 << RGU_STATUS2_USART0_RST_SHIFT) /* Activated by software */ #define RGU_STATUS2_UART1_RST_SHIFT (26) /* Bits 26-27: 27:26 Status of the UART1_RST reset generator output */ #define RGU_STATUS2_UART1_RST_MASK (3 << RGU_STATUS2_UART1_RST_SHIFT) # define RGU_STATUS2_UART1_RST_NONE (0 << RGU_STATUS2_UART1_RST_SHIFT) /* No reset activated */ # define RGU_STATUS2_UART1_RST_HW (1 << RGU_STATUS2_UART1_RST_SHIFT) /* Activated by reset generator */ # define RGU_STATUS2_UART1_RST_SW (3 << RGU_STATUS2_UART1_RST_SHIFT) /* Activated by software */ -#define RGU_STATUS2_UART2_RST_SHIFT (28) /* Bits 28-29: 29:28 Status of the UART2_RST reset generator output */ -#define RGU_STATUS2_UART2_RST_MASK (3 << RGU_STATUS2_UART2_RST_SHIFT) -# define RGU_STATUS2_UART2_RST_NONE (0 << RGU_STATUS2_UART2_RST_SHIFT) /* No reset activated */ -# define RGU_STATUS2_UART2_RST_HW (1 << RGU_STATUS2_UART2_RST_SHIFT) /* Activated by reset generator */ -# define RGU_STATUS2_UART2_RST_SW (3 << RGU_STATUS2_UART2_RST_SHIFT) /* Activated by software */ -#define RGU_STATUS2_UART3_RST_SHIFT (30) /* Bits 30-31: 31:30 Status of the UART3_RST reset generator output */ -#define RGU_STATUS2_UART3_RST_MASK (3 << RGU_STATUS2_UART3_RST_SHIFT) -# define RGU_STATUS2_UART3_RST_NONE (0 << RGU_STATUS2_UART3_RST_SHIFT) /* No reset activated */ -# define RGU_STATUS2_UART3_RST_HW (1 << RGU_STATUS2_UART3_RST_SHIFT) /* Activated by reset generator */ -# define RGU_STATUS2_UART3_RST_SW (3 << RGU_STATUS2_UART3_RST_SHIFT) /* Activated by software */ +#define RGU_STATUS2_USART2_RST_SHIFT (28) /* Bits 28-29: 29:28 Status of the USART2_RST reset generator output */ +#define RGU_STATUS2_USART2_RST_MASK (3 << RGU_STATUS2_USART2_RST_SHIFT) +# define RGU_STATUS2_USART2_RST_NONE (0 << RGU_STATUS2_USART2_RST_SHIFT) /* No reset activated */ +# define RGU_STATUS2_USART2_RST_HW (1 << RGU_STATUS2_USART2_RST_SHIFT) /* Activated by reset generator */ +# define RGU_STATUS2_USART2_RST_SW (3 << RGU_STATUS2_USART2_RST_SHIFT) /* Activated by software */ +#define RGU_STATUS2_USART3_RST_SHIFT (30) /* Bits 30-31: 31:30 Status of the USART3_RST reset generator output */ +#define RGU_STATUS2_USART3_RST_MASK (3 << RGU_STATUS2_USART3_RST_SHIFT) +# define RGU_STATUS2_USART3_RST_NONE (0 << RGU_STATUS2_USART3_RST_SHIFT) /* No reset activated */ +# define RGU_STATUS2_USART3_RST_HW (1 << RGU_STATUS2_USART3_RST_SHIFT) /* Activated by reset generator */ +# define RGU_STATUS2_USART3_RST_SW (3 << RGU_STATUS2_USART3_RST_SHIFT) /* Activated by software */ /* Reset status register 3 */ @@ -606,10 +606,10 @@ #define RGU_ACTIVE1_ADC1_RST (1 << 9) #define RGU_ACTIVE1_DAC_RST (1 << 10) /* Bit 11: Reserved */ -#define RGU_ACTIVE1_UART0_RST (1 << 12) +#define RGU_ACTIVE1_USART0_RST (1 << 12) #define RGU_ACTIVE1_UART1_RST (1 << 13) -#define RGU_ACTIVE1_UART2_RST (1 << 14) -#define RGU_ACTIVE1_UART3_RST (1 << 15) +#define RGU_ACTIVE1_USART2_RST (1 << 14) +#define RGU_ACTIVE1_USART3_RST (1 << 15) #define RGU_ACTIVE1_I2C0_RST (1 << 16) #define RGU_ACTIVE1_I2C1_RST (1 << 17) #define RGU_ACTIVE1_SSP0_RST (1 << 18) diff --git a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h index 8eb981f068..a90b4da64b 100644 --- a/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h +++ b/nuttx/arch/arm/src/lpc43xx/chip/lpc43_uart.h @@ -299,7 +299,7 @@ #define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */ #define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */ /* Bits 10-31: Reserved */ -/* ICA IrDA Control Register (UART0,2,3 only) */ +/* ICA IrDA Control Register (USART0,2,3 only) */ #define UART_ICR_IRDAEN (1 << 0) /* Bit 0: Enable IrDA mode */ #define UART_ICR_IRDAINV (1 << 1) /* Bit 1: Invert serial input */ diff --git a/nuttx/arch/arm/src/lpc43xx/lpc43_config.h b/nuttx/arch/arm/src/lpc43xx/lpc43_config.h new file mode 100644 index 0000000000..a71fec94a8 --- /dev/null +++ b/nuttx/arch/arm/src/lpc43xx/lpc43_config.h @@ -0,0 +1,109 @@ +/************************************************************************************ + * arch/arm/src/lpc43xx/lpc43_config.h + * + * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <gnutt@nuttx.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H +#define __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Are any UARTs enabled? */ + +#undef HAVE_UART +#if defined(CONFIG_LPC43_USART0) || defined(CONFIG_LPC43_UART1) || \ + defined(CONFIG_LPC43_USART2) || defined(CONFIG_LPC43_USART3) +# define HAVE_UART 1 +#endif + +/* Is there a serial console? There should be at most one defined. It could be on + * any UARTn, n=0,1,2,3 + */ + +#if defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_LPC43_USART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC43_UART1) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_LPC43_USART2) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_LPC43_USART3) +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# define HAVE_CONSOLE 1 +#else +# undef CONFIG_USART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_USART2_SERIAL_CONSOLE +# undef CONFIG_USART3_SERIAL_CONSOLE +# undef HAVE_CONSOLE +#endif + +/* Check UART flow control (Only supported by UART1) */ + +# undef CONFIG_USART0_FLOWCONTROL +# undef CONFIG_USART2_FLOWCONTROL +# undef CONFIG_USART3_FLOWCONTROL +#ifndef CONFIG_LPC43_UART1 +# undef CONFIG_UART1_FLOWCONTROL +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_LPC43XX_LPC43XX_CONFIG_H */ diff --git a/nuttx/configs/README.txt b/nuttx/configs/README.txt index 57a69f3be4..4937818ddd 100644 --- a/nuttx/configs/README.txt +++ b/nuttx/configs/README.txt @@ -1460,6 +1460,10 @@ configs/lpcxpresso-lpc1768 is based on the NXP LPC1768. The Code Red toolchain is used by default. STATUS: Under development. +configs/lpc4330-xplorer + NuttX port to the LPC4330-Xplorer board from NGX Technologies featuring + the NXP LPC4330FET100 MCU + configs/m68322evb This is a work in progress for the venerable m68322evb board from Motorola. This OS is also built with the arm-elf toolchain*. STATUS: diff --git a/nuttx/configs/lpc4330-xplorer/README.txt b/nuttx/configs/lpc4330-xplorer/README.txt index abb2a82381..26b4b1918e 100644 --- a/nuttx/configs/lpc4330-xplorer/README.txt +++ b/nuttx/configs/lpc4330-xplorer/README.txt @@ -1,7 +1,8 @@ README ^^^^^^ -README for NuttX port to the NGX LPC4330-Xplorer board +README for NuttX port to the LPC4330-Xplorer board from NGX Technologies +featuring the NXP LPC4330FET100 MCU Contents ^^^^^^^^ @@ -275,10 +276,10 @@ LPC4330-Xplorer Configuration Options CONFIG_LPC43_USBHOST=n CONFIG_LPC43_USBOTG=n CONFIG_LPC43_USBDEV=n - CONFIG_LPC43_UART0=y + CONFIG_LPC43_USART0=y CONFIG_LPC43_UART1=n - CONFIG_LPC43_UART2=n - CONFIG_LPC43_UART3=n + CONFIG_LPC43_USART2=n + CONFIG_LPC43_USART3=n CONFIG_LPC43_CAN1=n CONFIG_LPC43_CAN2=n CONFIG_LPC43_SPI=n @@ -304,16 +305,16 @@ LPC4330-Xplorer Configuration Options LPC43xx specific device driver settings - CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the - console and ttys0 (default is the UART0). - CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. + CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the UARTn for the + console and ttys0 (default is the USART0). + CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. This specific the size of the receive buffer - CONFIG_UARTn_TXBUFSIZE - Characters are buffered before + CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before being sent. This specific the size of the transmit buffer - CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be - CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. - CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity - CONFIG_UARTn_2STOP - Two stop bits + CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be + CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. + CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + CONFIG_U[S]ARTn_2STOP - Two stop bits LPC43xx specific CAN device driver settings. These settings all require CONFIG_CAN: diff --git a/nuttx/configs/lpc4330-xplorer/ostest/defconfig b/nuttx/configs/lpc4330-xplorer/ostest/defconfig index ea5e141a9a..8653cd5b32 100644 --- a/nuttx/configs/lpc4330-xplorer/ostest/defconfig +++ b/nuttx/configs/lpc4330-xplorer/ostest/defconfig @@ -73,7 +73,7 @@ CONFIG_ARCH=arm CONFIG_ARCH_ARM=y CONFIG_ARCH_CORTEXM4=y CONFIG_ARCH_CHIP=lpc43xx -CONFIG_ARCH_CHIP_LPC4320=y +CONFIG_ARCH_CHIP_LPC4330FET100=y CONFIG_ARCH_BOARD=lpc4330-xplorer CONFIG_ARCH_BOARD_LPC4330_XPLORER=y CONFIG_BOARD_LOOPSPERMSEC=7982 @@ -106,10 +106,10 @@ CONFIG_LPC43_ETHERNET=n CONFIG_LPC43_USBHOST=n CONFIG_LPC43_USBOTG=n CONFIG_LPC43_USBDEV=n -CONFIG_LPC43_UART0=y +CONFIG_LPC43_USART0=y CONFIG_LPC43_UART1=n -CONFIG_LPC43_UART2=n -CONFIG_LPC43_UART3=n +CONFIG_LPC43_USART2=n +CONFIG_LPC43_USART3=n CONFIG_LPC43_CAN1=n CONFIG_LPC43_CAN2=n CONFIG_LPC43_SPI=n @@ -135,51 +135,51 @@ CONFIG_LPC43_GPDMA=n # # LPC43xx specific serial device driver settings # -# CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the +# CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the UARTn for the # console and ttys0 (default is the UART1). -# CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. +# CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received. # This specific the size of the receive buffer -# CONFIG_UARTn_TXBUFSIZE - Characters are buffered before +# CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before # being sent. This specific the size of the transmit buffer -# CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be -# CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8. -# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity -# CONFIG_UARTn_2STOP - Two stop bits +# CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be +# CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8. +# CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity +# CONFIG_U[S]ARTn_2STOP - Two stop bits # -CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USART0_SERIAL_CONSOLE=y CONFIG_UART1_SERIAL_CONSOLE=n -CONFIG_UART2_SERIAL_CONSOLE=n -CONFIG_UART3_SERIAL_CONSOLE=n +CONFIG_USART2_SERIAL_CONSOLE=n +CONFIG_USART3_SERIAL_CONSOLE=n -CONFIG_UART0_TXBUFSIZE=256 +CONFIG_USART0_TXBUFSIZE=256 CONFIG_UART1_TXBUFSIZE=256 -CONFIG_UART2_TXBUFSIZE=256 -CONFIG_UART3_TXBUFSIZE=256 +CONFIG_USART2_TXBUFSIZE=256 +CONFIG_USART3_TXBUFSIZE=256 -CONFIG_UART0_RXBUFSIZE=256 +CONFIG_USART0_RXBUFSIZE=256 CONFIG_UART1_RXBUFSIZE=256 -CONFIG_UART2_RXBUFSIZE=256 -CONFIG_UART3_RXBUFSIZE=256 +CONFIG_USART2_RXBUFSIZE=256 +CONFIG_USART3_RXBUFSIZE=256 -CONFIG_UART0_BAUD=115200 -CONFIG_UART2_BAUD=115200 -CONFIG_UART3_BAUD=115200 +CONFIG_USART0_BAUD=115200 CONFIG_UART1_BAUD=115200 +CONFIG_USART2_BAUD=115200 +CONFIG_USART3_BAUD=115200 -CONFIG_UART0_BITS=8 +CONFIG_USART0_BITS=8 CONFIG_UART1_BITS=8 -CONFIG_UART2_BITS=8 -CONFIG_UART3_BITS=8 +CONFIG_USART2_BITS=8 +CONFIG_USART3_BITS=8 -CONFIG_UART0_PARITY=0 +CONFIG_USART0_PARITY=0 CONFIG_UART1_PARITY=0 -CONFIG_UART2_PARITY=0 -CONFIG_UART3_PARITY=0 +CONFIG_USART2_PARITY=0 +CONFIG_USART3_PARITY=0 -CONFIG_UART0_2STOP=0 +CONFIG_USART0_2STOP=0 CONFIG_UART1_2STOP=0 -CONFIG_UART2_2STOP=0 -CONFIG_UART3_2STOP=0 +CONFIG_USART2_2STOP=0 +CONFIG_USART3_2STOP=0 # # LPC43xx specific PHY/Ethernet device driver settings diff --git a/nuttx/configs/stm3210e-eval/include/board.h b/nuttx/configs/stm3210e-eval/include/board.h index 3e845d3aaa..8a479a7e54 100755 --- a/nuttx/configs/stm3210e-eval/include/board.h +++ b/nuttx/configs/stm3210e-eval/include/board.h @@ -314,19 +314,6 @@ EXTERN int stm32_lm75initialize(FAR const char *devpath); EXTERN xcpt_t stm32_lm75attach(xcpt_t irqhandler); #endif -/**************************************************************************** - * Name: up_pmbuttons - * - * Description: - * Configure all the buttons of the STM3210e-eval board as EXTI, - * so any button is able to wakeup the MCU from the PM_STANDBY mode - * - ****************************************************************************/ - -#if defined(CONFIG_PM) && defined(CONFIG_IDLE_CUSTOM) -EXTERN void up_pmbuttons(void); -#endif - #undef EXTERN #if defined(__cplusplus) } diff --git a/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h b/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h index e6bf825a90..ddfbee428e 100644 --- a/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h +++ b/nuttx/configs/stm3210e-eval/src/stm3210e-internal.h @@ -305,6 +305,19 @@ void stm32_deselectlcd(void); #endif /* CONFIG_STM32_FSMC */ /************************************************************************************ + * Name: up_pmbuttons + * + * Description: + * Configure all the buttons of the STM3210e-eval board as EXTI, so any button is + * able to wakeup the MCU from the PM_STANDBY mode + * + ************************************************************************************/ + +#if defined(CONFIG_PM) && defined(CONFIG_IDLE_CUSTOM) +EXTERN void up_pmbuttons(void); +#endif + +/************************************************************************************ * Name: up_unregisterbuttons * * Description: |