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2011-01-06target-arm: wire up the softfloat flush_input_to_zero flagPeter Maydell1-1/+7
Wire up the new softfloat support for flushing input denormals to zero on ARM. The FPSCR FZ bit enables flush-to-zero for both inputs and outputs, but the reporting of when inputs are flushed to zero is via a separate IDC bit rather than the UFC (underflow) bit used when output denormals are flushed to zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: Set softfloat cumulative exc flags from correct FPSCR bitsPeter Maydell1-1/+1
When handling a write to the ARM FPSCR, set the softfloat cumulative exception flags from the cumulative flags in the FPSCR, not the exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host will only look at the correct bits anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: fix SMMLA/SMMLS instructionsAurelien Jarno1-45/+51
SMMLA and SMMLS are broken on both in normal and thumb mode, that is both (different) implementations are wrong. They try to avoid a 64-bit add for the rounding, which is not trivial if you want to support both SMMLA and SMMLS with the same code. The code below uses the same implementation for both modes, using the code from the ARM manual. It also fixes the thumb decoding that was a mix between normal and thumb mode. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/629298 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-31target-arm: fix UMAAL instructionAurelien Jarno1-10/+22
UMAAL should use unsigned multiply instead of signed. This patch fixes this issue by handling UMAAL separately from UMULL/UMLAL/SMULL/SMLAL as these instructions are different enough. It also explicitly list instructions in case and catch nonexistent instruction as illegal. Also fixes a few style issues. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/696015 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9Juha Riihimäki1-0/+2
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: correct cp15 c1_sys reset value for cortex-a8Mattias Holm1-0/+1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: fix vmsav6 access controlJuha Riihimäki1-15/+19
Override access control checks (including execute) for mmu translation table descriptors assigned to manager domains. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Correct result in saturating cases for VQSHL of s8/16/32Peter Maydell1-3/+12
Where VQSHL of a signed 8/16/32 bit value saturated, the result value was not being calculated correctly (it should be either the minimum or maximum value for the size of the signed type). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: remove pointless else clause in VQSHL of u64Juha Riihimäki1-2/+0
Remove a pointless else clause in the neon_qshl_u64 helper. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix VQSHL of signed 64 bit values by shift counts >= 64Peter Maydell1-1/+1
VQSHL of a signed 64 bit non-zero value by a shift count >= 64 should saturate; return the correct value in this case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix VQSHL of signed 64 bit valuesJuha Riihimäki1-1/+1
Add a missing '-' which meant that we were misinterpreting the shift argument for VQSHL of 64 bit signed values and treating almost every shift value as if it were an extremely large right shift. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: Fix arguments passed to VQSHL helpersJuha Riihimäki1-2/+2
Correct the arguments passed when generating neon qshl_{u,s}64() helpers so that we use the correct registers. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: fix bug in translation of REVSHAurelien Jarno1-7/+3
The translation of REVSH shifted the low byte 8 steps left before performing an 8-bit sign extend, causing this part of the expression to alwas be 0. Reported-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-07ARM: Implement VCVT to 16 bit integer using new softfloat routinesPeter Maydell1-1/+1
Use the softfloat conversion routines for conversion to 16 bit integers, because just casting to a 16 bit type truncates the value rather than saturating it at 16-bit MAXINT/MININT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed pointPeter Maydell1-1/+1
VCVT of 16 bit fixed point to float should ignore the top 16 bits of the source register. Cast to int16_t and friends rather than int16 -- the former is guaranteed exactly 16 bits wide where the latter is merely at least 16 bits wide (and so is usually 32 bits). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for single<->double conversion of NaNPeter Maydell1-2/+10
The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for float-to-integer conversion of NaNPeter Maydell1-0/+27
The ARM architecture mandates that converting a NaN value to integer gives zero (if Invalid Operation FP exceptions are not being trapped). This isn't the behaviour of the SoftFloat library, so NaNs must be special-cased. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix sense of to_integer bit in Neon VCVT float/int conversionPeter Maydell1-4/+4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of Neon forms of VCVT between float and fixed pointPeter Maydell1-2/+6
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Fix decoding of VFP forms of VCVT between float and int/fixedPeter Maydell1-7/+12
Correct the decoding of source and destination registers for the VFP forms of the VCVT instructions which convert between floating point and integer or fixed-point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: fix ldrexd/strexdPeter Maydell1-3/+5
Correct ldrexd and strexd code to always read and write the high word of the 64-bit value from addr+4. Also make ldrexd and strexd agree that for a 64 bit value the address in env->exclusive_addr is that of the low word. This fixes the issues reported in https://bugs.launchpad.net/qemu/+bug/670883 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Handle 'smc' as an undefined instructionAdam Lackorzynski1-1/+8
Refine check on bkpt so that smc and undefined instruction encodings are handled as an undefined instruction and trap. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Fix mixup in decoding of saturating add and subJohan Bengtsson1-2/+2
The thumb2 decoder contained a mixup between the bit controlling doubling and the bit controlling if the operation was an add or a sub. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07target-arm: Add support for PKHxx in thumb2Johan Bengtsson1-18/+45
The PKHxx instructions were not recognized by the thumb2 decoder. The solution provided in this changeset is identical to the arm-mode implementation. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-03ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C codePeter Maydell2-0/+14
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C code as well as generated code, so we can use them to read and write the FPSCR when saving and restoring VFP registers across signal handlers in linux-user mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-12-03ARM: enable XScale/iWMMXT in linux-user modePeter Maydell1-0/+6
In linux-user mode, the XScale/iWMMXT coprocessors must be enabled at reset so that we can run code that uses these instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2010-12-03[PATCH] target-arm: remove unused functions cpu_lock(), cpu_unlock()Peter Maydell2-16/+0
Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil3-4/+5
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03remove exec-all.h inclusion from cpu.hPaolo Bonzini1-1/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2-5/+6
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-01target-arm : fix parallel saturated subtraction implementationChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-arm : fix thumb2 parallel add/sub opcode decodingChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-07-01target-arm: fix addsub/subadd implementationChih-Min Chao1-4/+4
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-11NEON vldN optimizationPaul Brook1-2/+4
When combining multiple values as part of a NEON array load, do explcit shift/or rather than using gen_bfi. This voids redundant mask operations. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-05-31arm: fix arm kernel boot for non zero start addrLars Munch1-1/+0
Booting an arm kernel has been broken a while when booting from non zero start address. This is due to the order of events: board init loads the kernel and sets register 15 to the start address and then qemu_system_reset reset the cpu making register 15 zero again. This patch fixes the usage of the register 15 start address trick in combination with arm_load_kernel. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-28arm: prevent coprocessor IO resetLars Munch1-7/+7
This prevent coprocessor IO structure from being reset on cpu reset. This was a problem for PXA which uses coprocessor 6 and 14. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25arm: remove dead assignments, spotted by clang analyzerBlue Swirl1-1/+0
Value stored is never read. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-08target-arm: fix neon vmon/vmvn with modified immediateJuha Riihimäki1-1/+1
Signed-Off-By: Riku Voipio <riku.voipio@nokia.com> Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08target-arm: resource leak fixes for iwmmxt disassembleLars Munch1-0/+2
This patch fixes few resource leaks in the iwmmxt disassemble. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05Fix arm-linux-userPaul Brook1-0/+2
Only include hw/loader.h from target-arm/helper.c when building for system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05ARMv7-M reset fixesPaul Brook2-10/+25
Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board reset routine to call this. Also load values directly from ROM as images have not been copied yet. Avoid clearing the NVIC pointer on cpu reset. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-27target-arm: disable PAGE_EXEC for XN pagesRabin Vincent1-3/+7
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection checking if the page is already in the TLB. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-23target-arm: Fix handling of AL condition in IT instructionJohan Bengtsson1-3/+5
Do not try to insert a conditional jump over next instruction when the condition code is AL as this will trigger an internal error. Signed-off-by: Johan Bengtsson <teofrastius@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-17Large page TLB flushPaul Brook1-21/+27
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-13target-arm: make RFE usable with any registerAdam Lackorzynski1-1/+1
The rfe instruction can be used with any register, not just sp. Adjust the condition check accordingly. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-5/+0
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson1-0/+3
Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-06target-arm: Fix missing 'return' in SRS handling.Adam Lackorzynski1-0/+1
There's a return missing in the srs handling which leads to srs always being treated an an invalid op. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon vshll instruction fixJuha Riihimäki1-0/+1
implementation only widened the 32bit source vector elements into a 64bit destination vector but forgot to perform the actual shifting operation. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHNRiku Voipio1-2/+2
The rounding/truncating options were inverted. truncating was done when rounding was meant and vice verse. Signed-off-by: Riku Voipio <riku.voipio@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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