diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2010-12-07 15:37:34 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2010-12-07 15:37:34 +0000 |
| commit | 2c9adbda721c9996ec6b371cac4a00c1164b818e (patch) | |
| tree | e2b26c30811dd0a35f069073929d427bd6fa3116 /target-arm | |
| parent | 49e14940adeea797abd2be4ccda97d0349b22aae (diff) | |
ARM: fix ldrexd/strexd
Correct ldrexd and strexd code to always read and write the
high word of the 64-bit value from addr+4.
Also make ldrexd and strexd agree that for a 64 bit value the
address in env->exclusive_addr is that of the low word.
This fixes the issues reported in
https://bugs.launchpad.net/qemu/+bug/670883
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/translate.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index bf1e643b5..7ee537537 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -5926,8 +5926,10 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, tcg_gen_mov_i32(cpu_exclusive_val, tmp); store_reg(s, rt, tmp); if (size == 3) { - tcg_gen_addi_i32(addr, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + TCGv tmp2 = new_tmp(); + tcg_gen_addi_i32(tmp2, addr, 4); + tmp = gen_ld32(tmp2, IS_USER(s)); + dead_tmp(tmp2); tcg_gen_mov_i32(cpu_exclusive_high, tmp); store_reg(s, rt2, tmp); } @@ -5987,7 +5989,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, if (size == 3) { TCGv tmp2 = new_tmp(); tcg_gen_addi_i32(tmp2, addr, 4); - tmp = gen_ld32(addr, IS_USER(s)); + tmp = gen_ld32(tmp2, IS_USER(s)); dead_tmp(tmp2); tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label); dead_tmp(tmp); |