| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2019-01-28 | clock-gen: Add BOM information + PDF exports of schematics | Harald Welte | 1 | -225/+2023 | |
| 2019-01-27 | clock-gen: Minor changes; final version as ordered | Harald Welte | 1 | -1/+1 | |
| * move DC jack to extend beyond PCB edge into front panel * harmonize component variants (10n only 0402, 4.7u only 0805) * add "sysmocom" as manufacturer name (WEEE requirement) | |||||
| 2019-01-27 | clock-gen: Cosmetic changes | Harald Welte | 1 | -966/+952 | |
| 2019-01-27 | clock-gen: finish routing of PCB layout | Harald Welte | 1 | -177/+771 | |
| 2019-01-26 | clock-gen: Connect EEPROM WP to GND to disable write-protect | Harald Welte | 1 | -0/+4 | |
| 2019-01-26 | clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing | Harald Welte | 1 | -23/+550 | |
| 2019-01-23 | clock-generator: Most of the layout | Harald Welte | 1 | -1577/+1909 | |
| Traces are intended for dual-layer 1mm FR4 PCB with 35um copper. | |||||
| 2019-01-23 | clock-generator: More schematics work; initial placement/grouping | Harald Welte | 1 | -0/+509 | |
| * add I2C EEPROM * start board design file * group parts to their respective "main part" * define TC-2030 pinout | |||||
| 2019-01-21 | clock-generator: More work on schematics (USB, UART, ESD) | Harald Welte | 1 | -57/+868 | |
| 2019-01-16 | initial check-in of upcoming clock-generator board | Harald Welte | 1 | -0/+4176 | |
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index : osmo-small-hardware | |
| Small Osmocom Hardware projects | Harald Welte |
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