| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2020-03-01 | clock-generator: Fix VDD connection of TC2050 SWD connector | Harald Welte | 1 | -3/+6 | |
| Closes: OS#4431 | |||||
| 2020-02-07 | clock-gen: increase I2C PU's to 4k7 | Martin Schramm | 1 | -12/+12 | |
| Although the SI5153 datasheet mentions the I2C PUs as ">=1k", this appears to be unusually strong for no obvious reason, and we don't have high data rates there... changed them to more reasonable 4k7. | |||||
| 2020-01-31 | clock-gen: update ATSAMD21's BOM attributes (solves OS#4387) | Martin Schramm | 1 | -8/+8 | |
| 2020-01-30 | clock-generator: exchange mini-USB foorprint (solves OS#4386) | Martin Schramm | 1 | -49/+19 | |
| ... and purge unneeded layers | |||||
| 2020-01-28 | clock-generator: exchange silk screen position of R14 vs. C19 | Martin Schramm | 1 | -2/+2 | |
| fortunately, they have a different size (0603 vs 0402), so while placing this be#came obvious. | |||||
| 2019-06-19 | clock-generator: Move GND via to avoid overlap with N$15 | Harald Welte | 1 | -6/+6 | |
| 2019-06-19 | <osmo-clock-gen: add more TVS for exposed signals, clean up and finish | Martin Schramm | 1 | -319/+566 | |
| 2019-06-19 | osmo-clock-gen: capacitive coupling for XA input needed - added 100n | Martin Schramm | 1 | -13/+27 | |
| This was a remark by tnt, thanks. | |||||
| 2019-06-19 | clock-generator: compacting + place MTA100 header (solves OSM#4050) | Martin Schramm | 1 | -487/+444 | |
| 2019-06-19 | clock-generator: changes adressing OSM#4050 | Martin Schramm | 1 | -1655/+1887 | |
| A shouded UEXT would need much space; no room for an MTA100 yet... tbd | |||||
| 2019-06-19 | clock-generator: insert changes discussed so far for v2 | Martin Schramm | 1 | -1552/+2217 | |
| * selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC) * use SAMD21 instead of SAMD11 * bring some GPIO on pin header * use GCLK_IO4 (PA10) to feed XA of PLL | |||||
| 2019-06-19 | clock-generator: add tracking LDO, make PCB four layer | Martin Schramm | 1 | -399/+529 | |
| 2019-06-19 | WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21 | Harald Welte | 1 | -152/+88 | |
| Closes: OS#3856 | |||||
| 2019-01-28 | clock-gen: Add BOM information + PDF exports of schematics | Harald Welte | 1 | -73/+903 | |
| 2019-01-27 | clock-gen: Minor changes; final version as ordered | Harald Welte | 1 | -39/+51 | |
| * move DC jack to extend beyond PCB edge into front panel * harmonize component variants (10n only 0402, 4.7u only 0805) * add "sysmocom" as manufacturer name (WEEE requirement) | |||||
| 2019-01-27 | clock-gen: Cosmetic changes | Harald Welte | 1 | -152/+225 | |
| 2019-01-27 | clock-gen: finish routing of PCB layout | Harald Welte | 1 | -265/+825 | |
| 2019-01-26 | clock-gen: Connect EEPROM WP to GND to disable write-protect | Harald Welte | 1 | -0/+2 | |
| 2019-01-26 | clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing | Harald Welte | 1 | -139/+370 | |
| 2019-01-23 | clock-generator: Most of the layout | Harald Welte | 1 | -516/+861 | |
| Traces are intended for dual-layer 1mm FR4 PCB with 35um copper. | |||||
| 2019-01-23 | clock-generator: More schematics work; initial placement/grouping | Harald Welte | 1 | -0/+1857 | |
| * add I2C EEPROM * start board design file * group parts to their respective "main part" * define TC-2030 pinout | |||||
 |
index : osmo-small-hardware | |
| Small Osmocom Hardware projects | Harald Welte |
| aboutsummaryrefslogtreecommitdiffstats |