diff options
| author | Harald Welte <laforge@osmocom.org> | 2021-07-05 21:52:15 +0200 |
|---|---|---|
| committer | Harald Welte <laforge@osmocom.org> | 2021-07-05 21:52:15 +0200 |
| commit | 8221a959b7317416c6c7e194e46e382d76a3d221 (patch) | |
| tree | a8b7b56cb9ece67997d507593c00a5560ca4691f | |
| parent | c9f7d03060346a39ed346f3faea8187dacf9e201 (diff) | |
add ncn8025-brekaout board
This is a small eval/breakout board for the NCN8025 smart card interface IC
| -rw-r--r-- | ncn8025-breakout/ncn8025-breakout.brd | 961 | ||||
| -rw-r--r-- | ncn8025-breakout/ncn8025-breakout.sch | 2196 |
2 files changed, 3157 insertions, 0 deletions
diff --git a/ncn8025-breakout/ncn8025-breakout.brd b/ncn8025-breakout/ncn8025-breakout.brd new file mode 100644 index 0000000..6bc3ba0 --- /dev/null +++ b/ncn8025-breakout/ncn8025-breakout.brd @@ -0,0 +1,961 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="7.7.0"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.05" unitdist="inch" unit="mm" style="lines" multiple="1" display="no" altdistance="0.3175" altunitdist="mm" altunit="mm"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> +<layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/> +<layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/> +<layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/> +<layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/> +<layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/> +<layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/> +<layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/> +<layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/> +<layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/> +<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/> +<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/> +<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/> +<layer number="18" name="Vias" color="2" fill="1" visible="yes" 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This minimum drill endsize can be set lower if needed. Values below 0.25mm will result in a higher DrillClassification. For details see the Eurocircuits Classification overview. +<p> +<u>Extra Notes:</u><br> +- The option <b>Distance-Copper/Dimension</b> is set to 0.25mm, the default for boards with a routed boardoutline. If you require Vcut on your board this parameter should be set to 0.45mm.<br> +- The option <b>Supply-Generate thermals for vias</b> is on by default but may be changed if required.<br> +- The option <b>Mask-Stop</b> is set to 0mm oversize which is the preffered value.<br> +- The option <b>Mask-Cream</b> is set to 0mm oversize by default, but may be changed if required<br> +- The option <b>Mask-Limit</b> is set to 0.45mm, resulting in covered or tented via holes for vias of 0.45mm and smaller. The option may be changed if required.<br> +- The options <b>Shapes</b> and <b>Misc</b> are not relevant. Values for <b>Shapes-Smds-Roundness</b> are not critical and can be set as you require. +<p> +<p> +You can set higher minimum values if you wish, setting lower minimum values is <u>not advisable</u>.<br> +If you need lower minimum values, please use a different Eurocircuits-EAGLE design rule file. For details see the Eurocircuits-EAGLE dru overview table. +<p> +Your Eurocircuits Team +</description> +<description language="en"> + +<p> +<b>Eurocircuits-EAGLE design rules</b><br> +<br> +Setup for <b>2-layer PatternClass6 BaseCopperO18 eCDefault</b> +<p> + The option <b>Sizes-Minimum Drill</b> is set to 0.35mm. This minimum drill endsize can be set lower if needed. Values below 0.25mm will result in a higher DrillClassification. For details see the Eurocircuits Classification overview. +<p> +<u>Extra Notes:</u><br> +- The option <b>Distance-Copper/Dimension</b> is set to 0.25mm, the default for boards with a routed boardoutline. If you require Vcut on your board this parameter should be set to 0.45mm.<br> +- The option <b>Supply-Generate thermals for vias</b> is on by default but may be changed if required.<br> +- The option <b>Mask-Stop</b> is set to 0mm oversize which is the preffered value.<br> +- The option <b>Mask-Cream</b> is set to 0mm oversize by default, but may be changed if required<br> +- The option <b>Mask-Limit</b> is set to 0.45mm, resulting in covered or tented via holes for vias of 0.45mm and smaller. The option may be changed if required.<br> +- The options <b>Shapes</b> and <b>Misc</b> are not relevant. Values for <b>Shapes-Smds-Roundness</b> are not critical and can be set as you require. +<p> +<p> +You can set higher minimum values if you wish, setting lower minimum values is <u>not advisable</u>.<br> +If you need lower minimum values, please use a different Eurocircuits-EAGLE design rule file. For details see the Eurocircuits-EAGLE dru overview table. +<p> +Your Eurocircuits Team +</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.018mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.018mm"/> +<param name="mtIsolate" value="1.55mm 0.71mm 0.36mm 0.2mm 0.2mm 0.2mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="0.4mm"/> +<param name="mdWirePad" value="0.3mm"/> +<param name="mdWireVia" value="0.3mm"/> +<param name="mdPadPad" value="0.15mm"/> +<param name="mdPadVia" value="0.15mm"/> +<param name="mdViaVia" value="0.15mm"/> +<param name="mdSmdPad" value="0mil"/> +<param name="mdSmdVia" value="0mil"/> +<param name="mdSmdSmd" value="0mil"/> +<param name="mdViaViaSameLayer" value="0.2mm"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" value="0.25mm"/> +<param name="mdDrill" value="0.35mm"/> +<param name="mdSmdStop" value="0mil"/> +<param name="msWidth" value="0.15mm"/> +<param name="msDrill" value="0.35mm"/> +<param name="msMicroVia" value="25mm"/> +<param name="msBlindViaRatio" value="0.5"/> +<param name="rvPadTop" value="0.25"/> +<param name="rvPadInner" value="0.25"/> +<param name="rvPadBottom" value="0.25"/> +<param name="rvViaOuter" value="0.25"/> +<param name="rvViaInner" value="0.25"/> +<param name="rvMicroViaOuter" value="0"/> +<param name="rvMicroViaInner" value="0"/> +<param name="rlMinPadTop" value="0.175mm"/> +<param name="rlMaxPadTop" value="2.5mm"/> +<param name="rlMinPadInner" value="0.175mm"/> +<param name="rlMaxPadInner" value="2.5mm"/> +<param name="rlMinPadBottom" value="0.175mm"/> +<param name="rlMaxPadBottom" value="2.5mm"/> +<param name="rlMinViaOuter" value="0.125mm"/> +<param name="rlMaxViaOuter" value="2.5mm"/> +<param name="rlMinViaInner" value="0.125mm"/> +<param name="rlMaxViaInner" value="2.5mm"/> +<param name="rlMinMicroViaOuter" value="2.5mm"/> +<param name="rlMaxMicroViaOuter" value="25mm"/> +<param name="rlMinMicroViaInner" value="2.5mm"/> +<param name="rlMaxMicroViaInner" value="25mm"/> +<param name="psTop" value="-1"/> +<param name="psBottom" value="-1"/> +<param name="psFirst" value="-1"/> +<param name="psElongationLong" value="100"/> +<param name="psElongationOffset" value="100"/> +<param name="mvStopFrame" value="0"/> +<param name="mvCreamFrame" value="0"/> +<param name="mlMinStopFrame" value="0mil"/> +<param name="mlMaxStopFrame" value="0mil"/> +<param name="mlMinCreamFrame" value="0mil"/> +<param name="mlMaxCreamFrame" value="0mil"/> +<param name="mlViaStopLimit" value="0.45mm"/> +<param name="srRoundness" value="0"/> +<param name="srMinRoundness" value="0mil"/> +<param name="srMaxRoundness" value="0mil"/> +<param name="slThermalIsolate" value="0.2mm"/> +<param name="slThermalsForVias" value="0"/> +<param name="dpMaxLengthDifference" value="10mm"/> +<param name="dpGapFactor" value="2.5"/> +<param name="checkGrid" value="0"/> +<param name="checkAngle" value="0"/> +<param name="checkFont" value="1"/> +<param name="checkRestrict" value="1"/> +<param name="useDiameter" value="13"/> +<param name="maxErrors" value="50"/> +</designrules> +<autorouter> +<pass name="Default"> +<param name="RoutingGrid" value="50mil"/> +<param name="AutoGrid" value="1"/> +<param name="Efforts" value="0"/> +<param name="TopRouterVariant" value="1"/> +<param name="tpViaShape" value="round"/> +<param name="PrefDir.1" value="a"/> +<param name="PrefDir.2" value="0"/> +<param name="PrefDir.3" value="0"/> +<param name="PrefDir.4" value="0"/> +<param name="PrefDir.5" value="0"/> +<param name="PrefDir.6" value="0"/> +<param name="PrefDir.7" value="0"/> +<param name="PrefDir.8" value="0"/> +<param name="PrefDir.9" value="0"/> +<param name="PrefDir.10" value="0"/> +<param name="PrefDir.11" value="0"/> +<param name="PrefDir.12" value="0"/> +<param name="PrefDir.13" value="0"/> +<param name="PrefDir.14" value="0"/> +<param name="PrefDir.15" value="0"/> +<param name="PrefDir.16" value="a"/> +<param name="cfVia" value="8"/> +<param name="cfNonPref" value="5"/> +<param name="cfChangeDir" value="2"/> +<param name="cfOrthStep" value="2"/> +<param name="cfDiagStep" value="3"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="1"/> +<param name="cfMalusStep" value="1"/> +<param name="cfPadImpact" value="4"/> +<param name="cfSmdImpact" value="4"/> +<param name="cfBusImpact" value="0"/> +<param name="cfHugging" value="3"/> +<param name="cfAvoid" value="4"/> +<param name="cfPolygon" value="10"/> +<param name="cfBase.1" value="0"/> +<param name="cfBase.2" value="1"/> +<param name="cfBase.3" value="1"/> +<param name="cfBase.4" value="1"/> +<param name="cfBase.5" value="1"/> +<param name="cfBase.6" value="1"/> +<param name="cfBase.7" value="1"/> +<param name="cfBase.8" value="1"/> +<param name="cfBase.9" value="1"/> +<param name="cfBase.10" value="1"/> +<param name="cfBase.11" value="1"/> +<param name="cfBase.12" value="1"/> +<param name="cfBase.13" value="1"/> +<param name="cfBase.14" value="1"/> +<param name="cfBase.15" value="1"/> +<param name="cfBase.16" value="0"/> +<param name="mnVias" value="20"/> +<param name="mnSegments" value="9999"/> +<param name="mnExtdSteps" value="9999"/> +<param name="mnRipupLevel" value="10"/> +<param name="mnRipupSteps" value="100"/> +<param name="mnRipupTotal" value="100"/> +</pass> +<pass name="Follow-me" refer="Default" active="yes"> +</pass> +<pass name="Busses" refer="Default" active="yes"> +<param name="cfNonPref" value="4"/> +<param name="cfBusImpact" value="4"/> +<param name="cfHugging" value="0"/> +<param name="mnVias" value="0"/> +</pass> +<pass name="Route" refer="Default" active="yes"> +</pass> +<pass name="Optimize1" refer="Default" active="yes"> +<param name="cfVia" value="99"/> +<param name="cfExtdStep" value="10"/> +<param name="cfHugging" value="1"/> +<param name="mnExtdSteps" value="1"/> +<param name="mnRipupLevel" value="0"/> +</pass> +<pass name="Optimize2" refer="Optimize1" active="yes"> +<param name="cfNonPref" value="0"/> +<param name="cfChangeDir" value="6"/> +<param name="cfExtdStep" value="0"/> +<param name="cfBonusStep" value="2"/> +<param name="cfMalusStep" value="2"/> +<param name="cfPadImpact" value="2"/> +<param name="cfSmdImpact" value="2"/> +<param name="cfHugging" value="0"/> +</pass> +<pass name="Optimize3" refer="Optimize2" active="yes"> +<param name="cfChangeDir" value="8"/> +<param name="cfPadImpact" value="0"/> +<param name="cfSmdImpact" value="0"/> +</pass> +<pass name="Optimize4" refer="Optimize3" active="yes"> +<param name="cfChangeDir" value="25"/> +</pass> +</autorouter> +<elements> +<element name="C1" library="rc-sysmocom" package="_0603" value="100n" x="49.2125" y="16.51" smashed="yes" rot="R90"> +<attribute name="NAME" x="48.26" y="16.51" size="1.016" layer="25" font="vector" ratio="14" rot="R90"/> +<attribute name="VALUE" x="50.7048" y="14.9225" size="0.508" layer="27" font="vector" ratio="10" rot="R90"/> +</element> +<element name="C2" library="rc-sysmocom" package="_0603" value="100n" x="49.53" y="25.4" smashed="yes" rot="R90"> +<attribute name="NAME" x="48.5775" y="23.8125" size="1.016" layer="25" font="vector" ratio="14" rot="R90"/> +<attribute name="VALUE" x="51.0223" y="23.8125" size="0.508" layer="27" font="vector" ratio="10" rot="R90"/> +</element> +<element name="C3" library="rc-sysmocom" package="_0603" value="10u" x="50.8" y="25.4" smashed="yes" rot="R90"> +<attribute name="NAME" x="52.705" y="23.8125" size="1.016" layer="25" font="vector" ratio="14" rot="R90"/> +<attribute name="VALUE" x="52.2923" y="23.8125" size="0.508" layer="27" font="vector" ratio="10" rot="R90"/> +</element> +<element name="C4" library="rc-sysmocom" package="_0603" value="100n" x="29.845" y="18.0975" smashed="yes"> +<attribute name="NAME" x="32.385" y="12.7" size="1.016" layer="25" font="vector" ratio="14"/> +<attribute name="VALUE" x="28.2575" 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+</elements> +<signals> +<signal name="VPP"> +<contactref element="SIM1" pad="C6"/> +</signal> +<signal name="GND"> +<contactref element="IC1" pad="EXPPAD"/> +<contactref element="C1" pad="1"/> +<contactref element="C3" pad="2"/> +<contactref element="C2" pad="2"/> +<contactref element="C7" pad="1"/> +<contactref element="C6" pad="1"/> +<contactref element="C5" pad="1"/> +<contactref element="C4" pad="1"/> +<contactref element="JP1" pad="2"/> +<contactref element="SIM1" pad="C5"/> +<contactref element="SIM1" pad="@2"/> +<contactref element="SIM1" pad="@3"/> +<contactref element="SIM1" pad="SW1"/> +<contactref element="JP2" pad="1"/> +<contactref element="JP3" pad="6"/> +<contactref element="C8" pad="2"/> +<polygon width="0.4064" layer="16"> +<vertex x="0" y="0"/> +<vertex x="0" y="40"/> +<vertex x="65" y="40"/> +<vertex x="65" y="0"/> +</polygon> +<via x="5" y="35" extent="1-16" drill="3.2" diameter="6.4516"/> +<via x="5" y="5" extent="1-16" drill="3.2" diameter="6.4516"/> +<via x="60" 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+</compatibility> +</eagle> diff --git a/ncn8025-breakout/ncn8025-breakout.sch b/ncn8025-breakout/ncn8025-breakout.sch new file mode 100644 index 0000000..67de3f1 --- /dev/null +++ b/ncn8025-breakout/ncn8025-breakout.sch @@ -0,0 +1,2196 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="7.7.0"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/> +<layers> +<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/> +<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/> +<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/> +<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/> +<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/> +<layer 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layer="95">>NAME</text> +<text x="5.08" y="-15.875" size="1.778" layer="96">>VALUE</text> +<pin name="VSEL1" x="-17.78" y="-10.16" visible="pin" length="middle" direction="in"/> +<pin name="CLKIN" x="-17.78" y="2.54" visible="pin" length="middle" direction="in"/> +<pin name="CLKDIV2" x="-17.78" y="-2.54" visible="pin" length="middle" direction="in"/> +<pin name="CCLK" x="17.78" y="-2.54" visible="pin" length="middle" direction="out" rot="R180"/> +<pin name="!CMDVCC" x="-17.78" y="12.7" visible="pin" length="middle" direction="in"/> +<pin name="CI/O" x="17.78" y="-5.08" visible="pin" length="middle" rot="R180"/> +<pin name="CLKDIV1" x="-17.78" y="0" visible="pin" length="middle" direction="in"/> +<pin name="VDDP" x="7.62" y="25.4" visible="pin" length="middle" direction="pwr" rot="R270"/> +<pin name="GND" x="0" y="-17.78" visible="pin" length="middle" direction="pwr" rot="R90"/> +<pin name="VDD" x="2.54" y="25.4" visible="pin" length="middle" direction="pwr" rot="R270"/> +<pin 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+<connect gate="G$1" pin="!PRES" pad="3"/> +<connect gate="G$1" pin="CCLK" pad="5"/> +<connect gate="G$1" pin="CI/O" pad="4"/> +<connect gate="G$1" pin="CLKDIV1" pad="14"/> +<connect gate="G$1" pin="CLKDIV2" pad="15"/> +<connect gate="G$1" pin="CLKIN" pad="12"/> +<connect gate="G$1" pin="CRST" pad="6"/> +<connect gate="G$1" pin="CVCC" pad="7"/> +<connect gate="G$1" pin="GND" pad="EXPPAD"/> +<connect gate="G$1" pin="IOUC" pad="13"/> +<connect gate="G$1" pin="RSTIN" pad="9"/> +<connect gate="G$1" pin="VDD" pad="10"/> +<connect gate="G$1" pin="VDDP" pad="2"/> +<connect gate="G$1" pin="VSEL0" pad="1"/> +<connect gate="G$1" pin="VSEL1" pad="16"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="supply1"> +<description><b>Supply Symbols</b><p> + GND, VCC, 0V, +5V, -5V, etc.<p> + Please keep in mind, that these devices are necessary for the + automatic wiring of the supply signals.<p> + The pin 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name="GND" prefix="GND"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="1" symbol="GND" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="VCC" prefix="P+"> +<description><b>SUPPLY SYMBOL</b></description> +<gates> +<gate name="VCC" symbol="VCC" x="0" y="0"/> +</gates> +<devices> +<device name=""> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="rc-sysmocom"> +<packages> +<package name="0805"> +<description><b>0805 (2012 Metric)</b></description> +<wire x1="-1.873" y1="0.883" x2="1.873" y2="0.883" width="0.0508" layer="39"/> +<wire x1="1.873" y1="-0.883" x2="-1.873" y2="-0.883" width="0.0508" layer="39"/> +<wire x1="-1.873" y1="-0.883" x2="-1.873" y2="0.883" width="0.0508" layer="39"/> +<wire x1="-0.381" y1="0.66" x2="0.381" y2="0.66" width="0.1016" layer="51"/> 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size="1.27" layer="27">>VALUE</text> +<rectangle x1="-1.651" y1="-1.3081" x2="-0.9009" y2="1.2918" layer="51"/> +<rectangle x1="0.9144" y1="-1.3081" x2="1.6645" y2="1.2918" layer="51"/> +<rectangle x1="-0.3" y1="-0.8999" x2="0.3" y2="0.8999" layer="35"/> +<polygon width="0.3048" layer="31"> +<vertex x="-1.905" y="1.11125"/> +<vertex x="-1.905" y="-1.11125"/> +<vertex x="-1.27" y="-1.11125"/> +<vertex x="-0.79375" y="0"/> +<vertex x="-1.27" y="1.11125"/> +</polygon> +<polygon width="0.3048" layer="31"> +<vertex x="1.905" y="1.11125"/> +<vertex x="1.905" y="-1.11125"/> +<vertex x="1.27" y="-1.11125"/> +<vertex x="0.79375" y="0"/> +<vertex x="1.27" y="1.11125"/> +</polygon> +</package> +</packages> +<symbols> +<symbol name="CAPACITOR"> +<wire x1="1.778" y1="0" x2="2.54" y2="0" width="0.1524" layer="94"/> +<wire x1="0" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/> +<text x="-1.524" y="2.54" size="1.27" layer="95">>NAME</text> +<text x="-1.524" y="-3.556" size="1.27" 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length="short" direction="pas" swaplevel="1" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="CAP_CERAMIC" prefix="C" uservalue="yes"> +<description><p><b>Ceramic Capacitors</b></p> +<b>0402</b> - 0402 Surface Mount Capacitors +<ul> +<li>16pF 50V 5% [Digikey: 445-4899-2-ND]</li> +<li>18pF 50V 5% [Digikey: 490-1281-2-ND]</li> +<li>22pF 50V 5% [Digikey: 490-1283-2-ND]</li> +<li>68pF 50V 5% [Digikey: 490-1289-2-ND]</li> +<li>0.1uF 10V 10% [Digikey: 490-1318-2-ND]</li> +<li>1.0uF 6.3V 10% [Digikey: 490-1320-2-ND]</li> +</ul> +<b>0603</b> - 0603 Surface Mount Capacitors +<ul> +<li>16 pF 50V 5% [Digikey: 445-5051-2-ND]</li> +<li>22 pF 50V [Digikey: PCC220ACVTR-ND]</li> +<li>33 pF 50V 5% [Digikey: 490-1415-1-ND]</li> +<li>56pF 50V 5% [Digikey: 490-1421-1-ND]</li> +<li>220pF 50V 5% [Digikey: 445-1285-1-ND]</li> +<li>680 pF 50V </li> +<li>2200 pF 50V 5% C0G [Digikey: 445-1297-1-ND]</li> +<li>5600 pF 100V 5% X7R [Digikey: 478-3711-1-ND]</li> +<li>0.1 µF 25V 10% [Digikey: PCC2277TR-ND]</li> +<li>0.22 µF 16V 10% X7R [Digikey: 445-1318-1-ND]</li> +<li>1.0 µF 25V 10% [Digikey: 445-5146-2-ND]</li> +</ul> +<b>0603</b> - RF Specific +<ul> +<li>3pF 250V +/-0.1pF RF [Digikey: 712-1347-1-ND]</li> +<li>18 pF 250V 5% [Digikey: 478-3505-1-ND or 712-1322-1-ND]</li> +<li>56 pF 250V 5% C0G RF [Digikey: 490-4867-1-ND]</li> +<li>68 pF 250V RF [Digikey: 490-4868-1-ND]</li> +</ul> +<b>0805</b> - 0805 Surface Mount Capacitors +<ul> +<li>220 pF 250V 2% <strong>RF</strong> Ceramic Capacitor [Digikey: 712-1398-1-ND]</li> +<li>1000 pF 50V 2% NP0 Ceramic Capacitor [Digikey: 478-3760-1-ND]</li> +<li>0.1 µF 25V 10% Ceramic Capacitor [Digikey: PCC1828TR-ND]</li> +<li>1.0 µF 16V 10% Ceramic Capacitor[Digikey: 490-1691-2-ND]</li> +<li>10.0 µF 10V 10% Ceramic Capacitor[Digikey: 709-1228-1-ND]</li> +<li>10.0 uF 16V 10% Ceramic Capacitor [Digikey: 478-5165-2-ND]</li> +<li>47 uF 6.3V 20% Ceramic Capacitor [Digikey: 587-1779-1-ND or 399-5506-1-ND]</li> +</ul> +</ul><b>1206</b> - 1206 Surface Mount Capacitors +<ul> +<li>47uF 10V 20% Ceramic Capacitor [Digikey: 490-5528-1-ND or 399-5508-1-ND or 445-6010-1-ND]</li> +<li>100uF 6.3V -20%, +80% Y5V Ceramic Capacitor (Digikey: 490-4512-1-ND, Mouser: 81-GRM31CF50J107ZE1L)</li> +</ul> +<b>1810</b> - 1810 Surface Mount Capacitors<br> +High volt MLC; no solder stop between for higher isolation</description> +<gates> +<gate name="G$1" symbol="CAPACITOR" x="0" y="-2.54"/> +</gates> +<devices> +<device name="0805" package="0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0603" package="0603"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0402" package="_0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0402MP" package="_0402MP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0603" package="_0603"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0603MP" package="_0603MP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0805" package="_0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0805MP" package="_0805MP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="CAP_HV_1808" package="C1808"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1210" package="C1210"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="-C1812" package="C1812K"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +<deviceset name="RESISTOR" prefix="R" uservalue="yes"> +<description><p><b>Resistors</b></p> +<b>0402</b> - 0402 Surface Mount Package +<ul> +<li>22 Ohm 1% 1/16W [Digikey: 311-22.0LRTR-ND]</li> +<li>33 Ohm 5% 1/16W</li> +<li>1.0K 5% 1/16W</li> +<li>1.5K 5% 1/16W</li> +<li>2.0K 1% 1/16W</li> +<li>10.0K 1% 1/16W [Digikey: 311-10.0KLRTR-ND]</li> +<li>10.0K 5% 1/16W [Digikey: RMCF0402JT10K0TR-ND]</li> +<li>12.1K 1% 1/16W [Digikey: 311-22.0LRTR-ND]</li> +<li>100.0K 5% 1/16W</li> +</ul> +<b>0603</b> - 0603 Surface Mount Package +<ul><li>1/10 Watt</li> +</ul> +<b>0805</b> - 0805 Surface Mount Package +<ul> +<li>1/8 Watt</li> +</ul> +<b>1206</b> - 1206 Surface Mount Package<br/> +<br/> +<b>2012</b> - 2010 Surface Mount Package +<ul><li>0.11 Ohm 1/2 Watt 1% Resistor - Digikey: RHM.11UCT-ND</li></ul></description> +<gates> +<gate name="G$1" symbol="RESISTOR" x="0" y="0"/> +</gates> +<devices> +<device name="0805" package="0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1206" package="1206"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0603" package="0603"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="0402" package="0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="2012" package="2012"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="2512" package="2512"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0402" package="_0402"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0402MP" package="_0402MP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0603" package="_0603"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0603MP" package="_0603MP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0805" package="_0805"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="_0805MP" package="_0805MP"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +<device name="1210" package="1210"> +<connects> +<connect gate="G$1" pin="1" pad="1"/> +<connect gate="G$1" pin="2" pad="2"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +<library name="laforge"> +<description><b>PCB Matrix Packages</b><p></description> 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x="5.08" y="2.54" visible="pad" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="5" x="-2.54" y="0" visible="pad" length="short" direction="pas" function="dot"/> +<pin name="6" x="5.08" y="0" visible="pad" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="7" x="-2.54" y="-2.54" visible="pad" length="short" direction="pas" function="dot"/> +<pin name="8" x="5.08" y="-2.54" visible="pad" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="9" x="-2.54" y="-5.08" visible="pad" length="short" direction="pas" function="dot"/> +<pin name="10" x="5.08" y="-5.08" visible="pad" length="short" direction="pas" function="dot" rot="R180"/> +<pin name="11" x="-2.54" y="-7.62" visible="pad" length="short" direction="pas" function="dot"/> +<pin name="12" x="5.08" y="-7.62" visible="pad" length="short" direction="pas" function="dot" rot="R180"/> +</symbol> +</symbols> +<devicesets> +<deviceset name="PINHD-2X6" prefix="JP" uservalue="yes"> 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pin="4" pad="4"/> +<connect gate="A" pin="5" pad="5"/> +<connect gate="A" pin="6" pad="6"/> +<connect gate="A" pin="7" pad="7"/> +<connect gate="A" pin="8" pad="8"/> +<connect gate="A" pin="9" pad="9"/> +</connects> +<technologies> +<technology name=""/> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="IC1" library="NCN8025" deviceset="NCN8025" device=""/> +<part name="GND1" library="supply1" deviceset="GND" device=""/> +<part name="C1" library="rc-sysmocom" deviceset="CAP_CERAMIC" device="_0603" value="100n"/> +<part name="GND2" library="supply1" deviceset="GND" device=""/> +<part name="C2" library="rc-sysmocom" deviceset="CAP_CERAMIC" device="_0603" value="100n"/> +<part name="C3" library="rc-sysmocom" deviceset="CAP_CERAMIC" device="_0603" value="10u"/> +<part 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deviceset="AMPHENOL_1010027182" device=""/> +<part name="GND15" library="supply1" deviceset="GND" device=""/> +<part name="GND10" library="supply1" deviceset="GND" device=""/> +<part name="GND11" library="supply1" deviceset="GND" device=""/> +<part name="R1" library="rc-sysmocom" deviceset="RESISTOR" device="_0603" value="15k"/> +<part name="R2" library="rc-sysmocom" deviceset="RESISTOR" device="_0603" value="15k"/> +<part name="P+1" library="supply1" deviceset="VCC" device=""/> +<part name="P+2" library="supply1" deviceset="VCC" device=""/> +<part name="GND12" library="supply1" deviceset="GND" device=""/> +<part name="P+3" library="supply1" deviceset="VCC" device=""/> +<part name="JP2" library="pinhead" deviceset="PINHD-2X6" device=""/> +<part name="JP3" library="laforge" deviceset="PINHD-1X6" device=""/> +<part name="GND13" library="supply1" deviceset="GND" device=""/> +<part name="C8" library="rc-sysmocom" deviceset="CAP_CERAMIC" device="_0603" value="10u"/> +<part name="GND16" library="supply1" deviceset="GND" device=""/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="IC1" gate="G$1" x="43.18" y="40.64"/> +<instance part="GND1" gate="1" x="43.18" y="12.7"/> +<instance part="C1" gate="G$1" x="38.1" y="73.66"/> +<instance part="GND2" gate="1" x="30.48" y="73.66" rot="R270"/> +<instance part="C2" gate="G$1" x="55.88" y="73.66"/> +<instance part="C3" gate="G$1" x="55.88" y="81.28"/> +<instance part="GND3" gate="1" x="63.5" y="81.28" rot="R90"/> +<instance part="GND4" gate="1" x="63.5" y="73.66" rot="R90"/> +<instance part="C4" gate="G$1" x="213.36" y="127" rot="R90"/> +<instance part="C5" gate="G$1" x="203.2" y="127" rot="R90"/> +<instance part="C6" gate="G$1" x="198.12" y="127" rot="R90"/> +<instance part="C7" gate="G$1" x="193.04" y="127" rot="R90"/> +<instance part="GND6" gate="1" x="193.04" y="121.92"/> +<instance part="GND7" gate="1" x="198.12" y="121.92"/> +<instance part="GND8" gate="1" x="203.2" y="121.92"/> +<instance part="GND9" gate="1" x="213.36" y="121.92"/> +<instance part="JP1" gate="G$1" x="60.96" y="96.52"/> +<instance part="GND14" gate="1" x="63.5" y="88.9" rot="R90"/> +<instance part="FRAME1" gate="G$1" x="0" y="0"/> +<instance part="FRAME1" gate="G$2" x="162.56" y="0"/> +<instance part="SIM1" gate="-HOLDER" x="231.14" y="162.56"/> +<instance part="SIM1" gate="-DETECT" x="134.62" y="45.72" rot="R90"/> +<instance part="SIM1" gate="-SHIELD" x="233.68" y="144.78"/> +<instance part="GND15" gate="1" x="254" y="106.68"/> +<instance part="GND10" gate="1" x="233.68" y="137.16"/> +<instance part="GND11" gate="1" x="134.62" y="38.1"/> +<instance part="R1" gate="G$1" x="134.62" y="63.5" rot="R90"/> +<instance part="R2" gate="G$1" x="152.4" y="137.16" rot="R90"/> +<instance part="P+1" gate="VCC" x="45.72" y="83.82"/> +<instance part="P+2" gate="VCC" x="134.62" y="73.66"/> +<instance part="GND12" gate="1" x="22.86" y="160.02" rot="R180"/> +<instance part="P+3" gate="VCC" x="40.64" y="160.02"/> +<instance part="JP2" gate="A" x="30.48" y="147.32"/> +<instance part="JP3" gate="A" x="124.46" y="149.86"/> +<instance part="GND13" gate="1" x="114.3" y="137.16"/> +<instance part="C8" gate="G$1" x="53.34" y="152.4"/> +<instance part="GND16" gate="1" x="60.96" y="152.4" rot="R90"/> +</instances> +<busses> +</busses> +<nets> +<net name="GND" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="GND"/> +<pinref part="GND1" gate="1" pin="GND"/> +<wire x1="43.18" y1="22.86" x2="43.18" y2="15.24" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C1" gate="G$1" pin="1"/> +<pinref part="GND2" gate="1" pin="GND"/> +<wire x1="33.02" y1="73.66" x2="35.56" y2="73.66" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="C3" gate="G$1" pin="2"/> +<pinref part="GND3" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="C2" gate="G$1" pin="2"/> +<pinref part="GND4" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="C7" gate="G$1" pin="1"/> +<pinref part="GND6" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="C6" gate="G$1" pin="1"/> +<pinref part="GND7" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="C5" gate="G$1" pin="1"/> +<pinref part="GND8" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="C4" gate="G$1" pin="1"/> +<pinref part="GND9" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="JP1" gate="G$1" pin="2"/> +<wire x1="58.42" y1="96.52" x2="53.34" y2="96.52" width="0.1524" layer="91"/> +<wire x1="53.34" y1="96.52" x2="53.34" y2="88.9" width="0.1524" layer="91"/> +<wire x1="53.34" y1="88.9" x2="60.96" y2="88.9" width="0.1524" layer="91"/> +<pinref part="GND14" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="SIM1" gate="-HOLDER" pin="GND"/> +<wire x1="246.38" y1="170.18" x2="254" y2="170.18" width="0.1524" layer="91"/> +<wire x1="254" y1="170.18" x2="254" y2="109.22" width="0.1524" layer="91"/> +<pinref part="GND15" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="SIM1" gate="-SHIELD" pin="SHLD"/> +<pinref part="GND10" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="SIM1" gate="-DETECT" pin="0@A"/> +<pinref part="GND11" gate="1" pin="GND"/> +</segment> +<segment> +<wire x1="27.94" y1="152.4" x2="22.86" y2="152.4" width="0.1524" layer="91"/> +<wire x1="22.86" y1="152.4" x2="22.86" y2="157.48" width="0.1524" layer="91"/> +<pinref part="GND12" gate="1" pin="GND"/> +<pinref part="JP2" gate="A" pin="1"/> +</segment> +<segment> +<pinref part="JP3" gate="A" pin="GND"/> +<wire x1="121.92" y1="144.78" x2="114.3" y2="144.78" width="0.1524" layer="91"/> +<wire x1="114.3" y1="144.78" x2="114.3" y2="139.7" width="0.1524" layer="91"/> +<pinref part="GND13" gate="1" pin="GND"/> +</segment> +<segment> +<pinref part="C8" gate="G$1" pin="2"/> +<pinref part="GND16" gate="1" pin="GND"/> +</segment> +</net> +<net name="VCC" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="VDD"/> +<wire x1="45.72" y1="66.04" x2="45.72" y2="73.66" width="0.1524" layer="91"/> +<pinref part="C1" gate="G$1" pin="2"/> +<wire x1="45.72" y1="73.66" x2="45.72" y2="81.28" width="0.1524" layer="91"/> +<wire x1="45.72" y1="73.66" x2="43.18" y2="73.66" width="0.1524" layer="91"/> +<junction x="45.72" y="73.66"/> +<pinref part="P+1" gate="VCC" pin="VCC"/> +</segment> +<segment> +<pinref part="R1" gate="G$1" pin="2"/> +<wire x1="134.62" y1="68.58" x2="134.62" y2="71.12" width="0.1524" layer="91"/> +<pinref part="P+2" gate="VCC" pin="VCC"/> +</segment> +<segment> +<wire x1="35.56" y1="152.4" x2="40.64" y2="152.4" width="0.1524" layer="91"/> +<wire x1="40.64" y1="152.4" x2="40.64" y2="157.48" width="0.1524" layer="91"/> +<pinref part="P+3" gate="VCC" pin="VCC"/> +<pinref part="JP2" gate="A" pin="2"/> +<pinref part="C8" gate="G$1" pin="1"/> +<wire x1="40.64" y1="152.4" x2="50.8" y2="152.4" width="0.1524" layer="91"/> +<junction x="40.64" y="152.4"/> +</segment> +</net> +<net name="5V" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="VDDP"/> +<wire x1="50.8" y1="66.04" x2="50.8" y2="73.66" width="0.1524" layer="91"/> +<pinref part="C3" gate="G$1" pin="1"/> +<wire x1="50.8" y1="73.66" x2="50.8" y2="81.28" width="0.1524" layer="91"/> +<wire x1="53.34" y1="81.28" x2="50.8" y2="81.28" width="0.1524" layer="91"/> +<pinref part="C2" gate="G$1" pin="1"/> +<wire x1="53.34" y1="73.66" x2="50.8" y2="73.66" width="0.1524" layer="91"/> +<junction x="50.8" y="73.66"/> +<junction x="50.8" y="81.28"/> +<pinref part="JP1" gate="G$1" pin="1"/> +<wire x1="58.42" y1="99.06" x2="50.8" y2="99.06" width="0.1524" layer="91"/> +<wire x1="50.8" y1="99.06" x2="50.8" y2="81.28" width="0.1524" layer="91"/> +<label x="50.8" y="99.06" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="USIM_IO" class="0"> +<segment> +<pinref part="SIM1" gate="-HOLDER" pin="I/O"/> +<wire x1="246.38" y1="165.1" x2="251.46" y2="165.1" width="0.1524" layer="91"/> +<wire x1="251.46" y1="165.1" x2="251.46" y2="154.94" width="0.1524" layer="91"/> +<wire x1="251.46" y1="154.94" x2="203.2" y2="154.94" width="0.1524" layer="91"/> +<pinref part="C5" gate="G$1" pin="2"/> +<wire x1="203.2" y1="154.94" x2="152.4" y2="154.94" width="0.1524" layer="91"/> +<wire x1="152.4" y1="154.94" x2="147.32" y2="154.94" width="0.1524" layer="91"/> +<wire x1="203.2" y1="154.94" x2="203.2" y2="132.08" width="0.1524" layer="91"/> +<junction x="203.2" y="154.94"/> +<label x="147.32" y="154.94" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="R2" gate="G$1" pin="2"/> +<wire x1="152.4" y1="154.94" x2="152.4" y2="142.24" width="0.1524" layer="91"/> +<junction x="152.4" y="154.94"/> +</segment> +<segment> +<pinref part="IC1" gate="G$1" pin="CI/O"/> +<wire x1="60.96" y1="35.56" x2="63.5" y2="35.56" width="0.1524" layer="91"/> +<label x="63.5" y="35.56" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="JP3" gate="A" pin="I/O"/> +<wire x1="121.92" y1="149.86" x2="114.3" y2="149.86" width="0.1524" layer="91"/> +<label x="114.3" y="149.86" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="USIM_VDD" class="0"> +<segment> +<pinref part="SIM1" gate="-HOLDER" pin="VCC"/> +<wire x1="218.44" y1="170.18" x2="213.36" y2="170.18" width="0.1524" layer="91"/> +<pinref part="C4" gate="G$1" pin="2"/> +<wire x1="213.36" y1="170.18" x2="157.48" y2="170.18" width="0.1524" layer="91"/> +<wire x1="157.48" y1="170.18" x2="147.32" y2="170.18" width="0.1524" layer="91"/> +<wire x1="213.36" y1="132.08" x2="213.36" y2="170.18" width="0.1524" layer="91"/> +<junction x="213.36" y="170.18"/> +<wire x1="157.48" y1="119.38" x2="157.48" y2="170.18" width="0.1524" layer="91"/> +<junction x="157.48" y="170.18"/> +<label x="147.32" y="170.18" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="R2" gate="G$1" pin="1"/> +<wire x1="152.4" y1="132.08" x2="152.4" y2="119.38" width="0.1524" layer="91"/> +<wire x1="152.4" y1="119.38" x2="157.48" y2="119.38" width="0.1524" layer="91"/> +</segment> +<segment> +<pinref part="IC1" gate="G$1" pin="CVCC"/> +<wire x1="60.96" y1="43.18" x2="63.5" y2="43.18" width="0.1524" layer="91"/> +<label x="63.5" y="43.18" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="JP3" gate="A" pin="VCC"/> +<wire x1="121.92" y1="157.48" x2="114.3" y2="157.48" width="0.1524" layer="91"/> +<label x="114.3" y="157.48" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="!USIM_RST" class="0"> +<segment> +<pinref part="SIM1" gate="-HOLDER" pin="RST"/> +<wire x1="218.44" y1="167.64" x2="198.12" y2="167.64" width="0.1524" layer="91"/> +<pinref part="C6" gate="G$1" pin="2"/> +<wire x1="198.12" y1="167.64" x2="147.32" y2="167.64" width="0.1524" layer="91"/> +<wire x1="198.12" y1="132.08" x2="198.12" y2="167.64" width="0.1524" layer="91"/> +<junction x="198.12" y="167.64"/> +<label x="147.32" y="167.64" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="IC1" gate="G$1" pin="CRST"/> +<wire x1="60.96" y1="40.64" x2="63.5" y2="40.64" width="0.1524" layer="91"/> +<label x="63.5" y="40.64" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="JP3" gate="A" pin="!RST"/> +<wire x1="121.92" y1="154.94" x2="114.3" y2="154.94" width="0.1524" layer="91"/> +<label x="114.3" y="154.94" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="USIM_CLK" class="0"> +<segment> +<pinref part="SIM1" gate="-HOLDER" pin="CLK"/> +<wire x1="218.44" y1="165.1" x2="193.04" y2="165.1" width="0.1524" layer="91"/> +<pinref part="C7" gate="G$1" pin="2"/> +<wire x1="193.04" y1="165.1" x2="147.32" y2="165.1" width="0.1524" layer="91"/> +<wire x1="193.04" y1="132.08" x2="193.04" y2="165.1" width="0.1524" layer="91"/> +<junction x="193.04" y="165.1"/> +<label x="147.32" y="165.1" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="IC1" gate="G$1" pin="CCLK"/> +<wire x1="60.96" y1="38.1" x2="63.5" y2="38.1" width="0.1524" layer="91"/> +<label x="63.5" y="38.1" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="JP3" gate="A" pin="CLK"/> +<wire x1="121.92" y1="152.4" x2="114.3" y2="152.4" width="0.1524" layer="91"/> +<label x="114.3" y="152.4" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="!USIM_PRESENT" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="!PRES"/> +<wire x1="60.96" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/> +<label x="63.5" y="48.26" size="1.27" layer="95" xref="yes"/> +</segment> +<segment> +<pinref part="SIM1" gate="-DETECT" pin="1@A"/> +<pinref part="R1" gate="G$1" pin="1"/> +<wire x1="134.62" y1="53.34" x2="134.62" y2="55.88" width="0.1524" layer="91"/> +<wire x1="134.62" y1="55.88" x2="134.62" y2="58.42" width="0.1524" layer="91"/> +<wire x1="134.62" y1="55.88" x2="124.46" y2="55.88" width="0.1524" layer="91"/> +<label x="124.46" y="55.88" size="1.27" layer="95" rot="R180" xref="yes"/> +<junction x="134.62" y="55.88"/> +</segment> +<segment> +<pinref part="JP3" gate="A" pin="VPP"/> +<wire x1="121.92" y1="147.32" x2="114.3" y2="147.32" width="0.1524" layer="91"/> +<label x="114.3" y="147.32" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="!INT" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="!INT"/> +<wire x1="25.4" y1="58.42" x2="20.32" y2="58.42" width="0.1524" layer="91"/> +<label x="20.32" y="58.42" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="JP2" gate="A" pin="11"/> +<wire x1="27.94" y1="139.7" x2="20.32" y2="139.7" width="0.1524" layer="91"/> +<label x="20.32" y="139.7" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +</net> +<net name="RSTIN" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="RSTIN"/> +<wire x1="25.4" y1="55.88" x2="20.32" y2="55.88" width="0.1524" layer="91"/> +<label x="20.32" y="55.88" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="JP2" gate="A" pin="12"/> +<wire x1="35.56" y1="139.7" x2="43.18" y2="139.7" width="0.1524" layer="91"/> +<label x="43.18" y="139.7" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="!CMDVCC" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="!CMDVCC"/> +<wire x1="25.4" y1="53.34" x2="20.32" y2="53.34" width="0.1524" layer="91"/> +<label x="20.32" y="53.34" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<pinref part="JP2" gate="A" pin="4"/> +<wire x1="35.56" y1="149.86" x2="43.18" y2="149.86" width="0.1524" layer="91"/> +<label x="43.18" y="149.86" size="1.27" layer="95" xref="yes"/> +</segment> +</net> +<net name="IOUC" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="IOUC"/> +<wire x1="25.4" y1="48.26" x2="20.32" y2="48.26" width="0.1524" layer="91"/> +<label x="20.32" y="48.26" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="27.94" y1="142.24" x2="20.32" y2="142.24" width="0.1524" layer="91"/> +<label x="20.32" y="142.24" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="JP2" gate="A" pin="9"/> +</segment> +</net> +<net name="CLKIN" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="CLKIN"/> +<wire x1="25.4" y1="43.18" x2="20.32" y2="43.18" width="0.1524" layer="91"/> +<label x="20.32" y="43.18" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="35.56" y1="142.24" x2="43.18" y2="142.24" width="0.1524" layer="91"/> +<label x="43.18" y="142.24" size="1.27" layer="95" xref="yes"/> +<pinref part="JP2" gate="A" pin="10"/> +</segment> +</net> +<net name="CLKDIV1" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="CLKDIV1"/> +<wire x1="25.4" y1="40.64" x2="20.32" y2="40.64" width="0.1524" layer="91"/> +<label x="20.32" y="40.64" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="35.56" y1="144.78" x2="43.18" y2="144.78" width="0.1524" layer="91"/> +<label x="43.18" y="144.78" size="1.27" layer="95" xref="yes"/> +<pinref part="JP2" gate="A" pin="8"/> +</segment> +</net> +<net name="CLKDIV2" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="CLKDIV2"/> +<wire x1="25.4" y1="38.1" x2="20.32" y2="38.1" width="0.1524" layer="91"/> +<label x="20.32" y="38.1" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="27.94" y1="144.78" x2="20.32" y2="144.78" width="0.1524" layer="91"/> +<label x="20.32" y="144.78" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="JP2" gate="A" pin="7"/> +</segment> +</net> +<net name="VSEL0" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="VSEL0"/> +<wire x1="25.4" y1="33.02" x2="20.32" y2="33.02" width="0.1524" layer="91"/> +<label x="20.32" y="33.02" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="27.94" y1="147.32" x2="20.32" y2="147.32" width="0.1524" layer="91"/> +<label x="20.32" y="147.32" size="1.27" layer="95" rot="R180" xref="yes"/> +<pinref part="JP2" gate="A" pin="5"/> +</segment> +</net> +<net name="VSEL1" class="0"> +<segment> +<pinref part="IC1" gate="G$1" pin="VSEL1"/> +<wire x1="25.4" y1="30.48" x2="20.32" y2="30.48" width="0.1524" layer="91"/> +<label x="20.32" y="30.48" size="1.27" layer="95" rot="R180" xref="yes"/> +</segment> +<segment> +<wire x1="35.56" y1="147.32" x2="43.18" y2="147.32" width="0.1524" layer="91"/> +<label x="43.18" y="147.32" size="1.27" layer="95" xref="yes"/> +<pinref part="JP2" gate="A" pin="6"/> +</segment> +</net> +</nets> +</sheet> +</sheets> +<errors> +<approved hash="104,1,50.8,66.04,IC1,VDDP,5V,,,"/> +<approved hash="104,1,45.72,66.04,IC1,VDD,VCC,,,"/> +<approved hash="104,1,60.96,43.18,IC1,CVCC,USIM_VDD,,,"/> +<approved hash="104,1,218.44,170.18,SIM1-HOLDER,VCC,USIM_VDD,,,"/> +<approved hash="204,1,246.38,167.64,SIM1-HOLDER,VPP,,,,"/> +<approved hash="104,1,121.92,157.48,JP3,VCC,USIM_VDD,,,"/> +<approved hash="104,1,121.92,147.32,JP3,VPP,!USIM_PRESENT,,,"/> +<approved hash="206,1,60.96,40.64,!USIM_RST,,,,,"/> +<approved hash="206,1,121.92,154.94,!USIM_RST,,,,,"/> +<approved hash="206,1,60.96,38.1,USIM_CLK,,,,,"/> +<approved hash="206,1,121.92,152.4,USIM_CLK,,,,,"/> +</errors> +</schematic> +</drawing> +</eagle> |