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-rw-r--r--fpga/hw-v2/diamond/.run_manager.ini9
-rw-r--r--fpga/hw-v2/diamond/.setting.ini4
-rw-r--r--fpga/hw-v2/diamond/Strategy1.sty7
-rw-r--r--fpga/hw-v2/diamond/reportview.xml10
-rw-r--r--fpga/hw-v2/diamond/usbrx_vhdl.ldf68
-rw-r--r--fpga/hw-v2/diamond/usbrx_vhdl.lpf130
-rw-r--r--fpga/hw-v2/diamond/usbrx_vhdl.pty3
7 files changed, 231 insertions, 0 deletions
diff --git a/fpga/hw-v2/diamond/.run_manager.ini b/fpga/hw-v2/diamond/.run_manager.ini
new file mode 100644
index 0000000..bf1b20d
--- /dev/null
+++ b/fpga/hw-v2/diamond/.run_manager.ini
@@ -0,0 +1,9 @@
+[Runmanager]
+Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\x1\0\0)
+windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
+headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x13\0\xfc\a\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\f\0\0\0\x64\0\0\0\v\0\0\0\x64\0\0\0\n\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x3\xa7\0\0\0\x13\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x3\x84\0\0\0\t\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
+
+[usbrx_vhdl%3CStrategy1%3E]
+isChecked=false
+isHidden=false
+isExpanded=false
diff --git a/fpga/hw-v2/diamond/.setting.ini b/fpga/hw-v2/diamond/.setting.ini
new file mode 100644
index 0000000..180a0c1
--- /dev/null
+++ b/fpga/hw-v2/diamond/.setting.ini
@@ -0,0 +1,4 @@
+[General]
+PAR.auto_tasks=PARTrace, IOTiming
+Map.auto_tasks=@Invalid()
+Export.auto_tasks=TimingSimFileVHD, Bitgen
diff --git a/fpga/hw-v2/diamond/Strategy1.sty b/fpga/hw-v2/diamond/Strategy1.sty
new file mode 100644
index 0000000..5c3e268
--- /dev/null
+++ b/fpga/hw-v2/diamond/Strategy1.sty
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label="Strategy1">
+ <Property name="PROP_MAP_TimingDriven" value="True" time="0"/>
+ <Property name="PROP_MAP_TimingDrivenNodeRep" value="True" time="0"/>
+ <Property name="PROP_MAP_TimingDrivenPack" value="True" time="0"/>
+</Strategy>
diff --git a/fpga/hw-v2/diamond/reportview.xml b/fpga/hw-v2/diamond/reportview.xml
new file mode 100644
index 0000000..c1a5034
--- /dev/null
+++ b/fpga/hw-v2/diamond/reportview.xml
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE Report>
+<ReportView version="2.0">
+ <Implement name="usbrx_vhdl">
+ <ToolReport id="toolhle_genhierarchy" path="hdldiagram_gen_hierarchy.html" status="2"/>
+ <ToolReport id="toolhle_runbkm" path="" status="2"/>
+ <ToolReport id="toolpio" path="" status="2"/>
+ <ToolReport id="toolsso" path="" status="2"/>
+ </Implement>
+</ReportView>
diff --git a/fpga/hw-v2/diamond/usbrx_vhdl.ldf b/fpga/hw-v2/diamond/usbrx_vhdl.ldf
new file mode 100644
index 0000000..cdf9ed2
--- /dev/null
+++ b/fpga/hw-v2/diamond/usbrx_vhdl.ldf
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="1.3" title="usbrx_vhdl" device="LFXP2-5E-5M132C" default_implementation="usbrx_vhdl">
+ <Options/>
+ <Implementation title="usbrx_vhdl" dir="usbrx_vhdl" description="usbrx_vhdl" default_strategy="Strategy1">
+ <Options top="usbrx_toplevel"/>
+ <Source name="../src/mt_toolbox/mt_toolbox.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/toplevel/usbrx_clkgen.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/toplevel/usbrx_toplevel.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/toplevel/usbrx_pwm.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/toplevel/usbrx_regbank.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/toplevel/usbrx_spi.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/mt_filter/mt_filter.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/filter/usbrx_halfband.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/datapath/usbrx_ssc.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/datapath/usbrx_ad7357.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/datapath/usbrx_decimate.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/datapath/usbrx_offset.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/usbrx/usbrx.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/mt_filter/mt_fil_mac_slow.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/mt_filter/mt_fil_storage_slow.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/mt_filter/mt_fir_symmetric_slow.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../src/mt_toolbox/mt_clktools.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../deploy/usbrx.xcf" type="ispVM Download Project" type_short="ispVM" excluded="TRUE">
+ <Options/>
+ </Source>
+ <Source name="usbrx_vhdl.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+ <Source name="usbrx_vhdl/usbrx_vhdl.xcf" type="ispVM Download Project" type_short="ispVM">
+ <Options/>
+ </Source>
+ </Implementation>
+ <Strategy name="Strategy1" file="Strategy1.sty"/>
+</BaliProject>
diff --git a/fpga/hw-v2/diamond/usbrx_vhdl.lpf b/fpga/hw-v2/diamond/usbrx_vhdl.lpf
new file mode 100644
index 0000000..d997a99
--- /dev/null
+++ b/fpga/hw-v2/diamond/usbrx_vhdl.lpf
@@ -0,0 +1,130 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "clk_in_pclk" SITE "H1" ;
+LOCATE COMP "adc_cs" SITE "G1" ;
+LOCATE COMP "adc_sck" SITE "B1" ;
+LOCATE COMP "adc_sd1" SITE "D1" ;
+LOCATE COMP "adc_sd2" SITE "E1" ;
+LOCATE COMP "ctl_int" SITE "P2" ;
+LOCATE COMP "ctl_cs" SITE "P4" ;
+LOCATE COMP "ctl_sck" SITE "P5" ;
+LOCATE COMP "ctl_mosi" SITE "P6" ;
+LOCATE COMP "ctl_miso" SITE "P7" ;
+LOCATE COMP "dingsrst" SITE "P10" ;
+LOCATE COMP "dings" SITE "P9" ;
+LOCATE COMP "rx_clk" SITE "B14" ;
+LOCATE COMP "rx_syn" SITE "D14" ;
+LOCATE COMP "rx_dat" SITE "E14" ;
+LOCATE COMP "tx_clk" SITE "A14" ;
+LOCATE COMP "tx_syn" SITE "G14" ;
+LOCATE COMP "tx_dat" SITE "F14" ;
+LOCATE COMP "gain0" SITE "P1" ;
+LOCATE COMP "gain1" SITE "N1" ;
+LOCATE COMP "gps_1pps" SITE "P14" ;
+LOCATE COMP "gps_10k" SITE "N14" ;
+LOCATE COMP "gpio_0" SITE "A1" ;
+LOCATE COMP "gpio_1" SITE "A2" ;
+LOCATE COMP "gpio_2" SITE "A3" ;
+LOCATE COMP "gpio_3" SITE "A5" ;
+LOCATE COMP "gpio_4" SITE "A7" ;
+LOCATE COMP "gpio_5" SITE "A8" ;
+LOCATE COMP "gpio_6" SITE "A9" ;
+LOCATE COMP "gpio_7" SITE "A10" ;
+LOCATE COMP "gpio_8" SITE "A11" ;
+LOCATE COMP "gpio_9" SITE "A13" ;
+LOCATE COMP "vgnd_0" SITE "B3" ;
+LOCATE COMP "vgnd_1" SITE "C5" ;
+LOCATE COMP "vgnd_2" SITE "C8" ;
+LOCATE COMP "vgnd_3" SITE "B2" ;
+LOCATE COMP "vgnd_4" SITE "C2" ;
+LOCATE COMP "vgnd_5" SITE "D2" ;
+LOCATE COMP "vgnd_6" SITE "M6" ;
+LOCATE COMP "vgnd_7" SITE "N2" ;
+LOCATE COMP "vgnd_8" SITE "N3" ;
+LOCATE COMP "vgnd_9" SITE "D12" ;
+LOCATE COMP "vgnd_10" SITE "D13" ;
+LOCATE COMP "vgnd_11" SITE "M10" ;
+LOCATE COMP "vcc33_0" SITE "B6" ;
+LOCATE COMP "vcc33_1" SITE "C7" ;
+LOCATE COMP "vcc33_2" SITE "C10" ;
+LOCATE COMP "vcc33_3" SITE "D3" ;
+LOCATE COMP "vcc33_4" SITE "E3" ;
+LOCATE COMP "vcc33_5" SITE "G2" ;
+LOCATE COMP "vcc33_6" SITE "H2" ;
+LOCATE COMP "vcc33_7" SITE "M4" ;
+LOCATE COMP "vcc33_8" SITE "M5" ;
+LOCATE COMP "vcc33_9" SITE "P13" ;
+LOCATE COMP "vcc33_10" SITE "M13" ;
+LOCATE COMP "vcc33_11" SITE "N13" ;
+LOCATE COMP "vcc12_0" SITE "B9" ;
+LOCATE COMP "vcc12_1" SITE "B10" ;
+LOCATE COMP "vcc12_2" SITE "C9" ;
+LOCATE COMP "vcc12_3" SITE "H13" ;
+LOCATE COMP "vcc12_4" SITE "H14" ;
+
+IOBUF PORT "clk_in_pclk" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "adc_cs" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "adc_sck" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "adc_sd1" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "adc_sd2" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ctl_int" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "ctl_cs" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ctl_sck" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ctl_mosi" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "ctl_miso" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "dingsrst" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "dings" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gps_10k" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "rx_clk" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "rx_syn" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "rx_dat" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "tx_clk" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "tx_syn" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "tx_dat" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gain0" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gain1" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gps_1pps" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_2" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_3" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_4" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_7" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_8" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_0" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_1" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_2" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_3" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_4" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_5" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_6" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_7" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_8" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_9" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_10" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vgnd_11" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_0" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_1" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_2" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_3" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_4" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_5" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_6" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_7" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_8" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_9" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_10" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_11" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc33_12" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc12_0" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc12_1" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc12_2" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc12_3" IO_TYPE=LVCMOS33 DRIVE=4 ;
+IOBUF PORT "vcc12_4" IO_TYPE=LVCMOS33 DRIVE=4 ;
+
+FREQUENCY PORT "clk_in_pclk" 30.000000 MHz ;
+FREQUENCY NET "clk_80_c" 80.000000 MHz ;
+SYSCONFIG INBUF=OFF ;
diff --git a/fpga/hw-v2/diamond/usbrx_vhdl.pty b/fpga/hw-v2/diamond/usbrx_vhdl.pty
new file mode 100644
index 0000000..537921f
--- /dev/null
+++ b/fpga/hw-v2/diamond/usbrx_vhdl.pty
@@ -0,0 +1,3 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE strategy>
+<Strategy version="1.0" predefined="0" description="" label=""/>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-28 08:50:06 +0000