diff options
Diffstat (limited to 'fpga/hw-v2/diamond/usbrx_vhdl.ldf')
| -rw-r--r-- | fpga/hw-v2/diamond/usbrx_vhdl.ldf | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/fpga/hw-v2/diamond/usbrx_vhdl.ldf b/fpga/hw-v2/diamond/usbrx_vhdl.ldf new file mode 100644 index 0000000..cdf9ed2 --- /dev/null +++ b/fpga/hw-v2/diamond/usbrx_vhdl.ldf @@ -0,0 +1,68 @@ +<?xml version="1.0" encoding="UTF-8"?> +<BaliProject version="1.3" title="usbrx_vhdl" device="LFXP2-5E-5M132C" default_implementation="usbrx_vhdl"> + <Options/> + <Implementation title="usbrx_vhdl" dir="usbrx_vhdl" description="usbrx_vhdl" default_strategy="Strategy1"> + <Options top="usbrx_toplevel"/> + <Source name="../src/mt_toolbox/mt_toolbox.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/toplevel/usbrx_clkgen.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/toplevel/usbrx_toplevel.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/toplevel/usbrx_pwm.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/toplevel/usbrx_regbank.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/toplevel/usbrx_spi.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/mt_filter/mt_filter.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/filter/usbrx_halfband.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/datapath/usbrx_ssc.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/datapath/usbrx_ad7357.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/datapath/usbrx_decimate.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/datapath/usbrx_offset.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/usbrx/usbrx.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/mt_filter/mt_fil_mac_slow.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/mt_filter/mt_fil_storage_slow.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/mt_filter/mt_fir_symmetric_slow.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../src/mt_toolbox/mt_clktools.vhd" type="VHDL" type_short="VHDL"> + <Options/> + </Source> + <Source name="../deploy/usbrx.xcf" type="ispVM Download Project" type_short="ispVM" excluded="TRUE"> + <Options/> + </Source> + <Source name="usbrx_vhdl.lpf" type="Logic Preference" type_short="LPF"> + <Options/> + </Source> + <Source name="usbrx_vhdl/usbrx_vhdl.xcf" type="ispVM Download Project" type_short="ispVM"> + <Options/> + </Source> + </Implementation> + <Strategy name="Strategy1" file="Strategy1.sty"/> +</BaliProject> |