diff options
| author | Christian Daniel <cd@maintech.de> | 2012-05-17 22:18:26 +0200 |
|---|---|---|
| committer | Christian Daniel <cd@maintech.de> | 2012-05-17 22:18:26 +0200 |
| commit | c62f5734b7742952a2dbc754be35db35aee54c26 (patch) | |
| tree | a8c886ee4eca9c243cce30726bf68b5ed31d0ae4 /fpga/hw-v2/compile.cfg | |
| parent | 0f007d876a9d5fc40715aafa7ec284294eff6b70 (diff) | |
added fpga source and project files for hardware v2
Diffstat (limited to 'fpga/hw-v2/compile.cfg')
| -rw-r--r-- | fpga/hw-v2/compile.cfg | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/fpga/hw-v2/compile.cfg b/fpga/hw-v2/compile.cfg new file mode 100644 index 0000000..410fac9 --- /dev/null +++ b/fpga/hw-v2/compile.cfg @@ -0,0 +1,46 @@ +[View]
+Entity=
+Architecture=
+TopLevelType=
+[file:.\src\usbrx\toplevel\usbrx_toplevel.vhd]
+Enabled=1
+[file:.\src\usbrx\toplevel\usbrx_clkgen.vhd]
+Enabled=1
+[file:.\src\mt_toolbox\mt_toolbox.vhd]
+Enabled=1
+[file:.\src\usbrx\toplevel\usbrx_spi.vhd]
+Enabled=1
+[file:.\src\usbrx\toplevel\usbrx_regbank.vhd]
+Enabled=1
+[file:.\src\testbench\tb_usbrx.vhd]
+Enabled=1
+VerilogLanguage=7
+LIB=
+[file:.\src\usbrx\toplevel\usbrx_pwm.vhd]
+Enabled=1
+[file:.\src\mt_filter\mt_filter.vhd]
+Enabled=1
+[file:.\src\usbrx\filter\usbrx_halfband.vhd]
+Enabled=1
+[file:.\src\usbrx\datapath\usbrx_decimate.vhd]
+Enabled=1
+[file:.\src\usbrx\datapath\usbrx_ad7357.vhd]
+Enabled=1
+[file:.\src\usbrx\datapath\usbrx_ssc.vhd]
+Enabled=1
+[file:.\src\usbrx\usbrx.vhd]
+Enabled=1
+[file:.\src\usbrx\datapath\usbrx_offset.vhd]
+Enabled=1
+[file:.\src\mt_filter\mt_fil_storage_slow.vhd]
+Enabled=1
+[file:.\src\mt_filter\mt_fil_mac_slow.vhd]
+Enabled=1
+[file:.\src\mt_filter\mt_fir_symmetric_slow.vhd]
+Enabled=1
+[file:.\src\mt_toolbox\mt_clktools.vhd]
+Enabled=1
+[file:.\src\testbench\tb_filter.vhd]
+LIB=
+Enabled=1
+VerilogLanguage=7
|