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path: root/target-xtensa/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov1-0/+12
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov1-0/+6
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov1-0/+9
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov1-0/+15
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov1-0/+1
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov1-0/+6
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov1-0/+3
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov1-1/+5
2011-10-15target-xtensa: implement MAC16 optionMax Filippov1-0/+3
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov1-0/+1
2011-09-10target-xtensa: implement boolean optionMax Filippov1-0/+1
2011-09-10target-xtensa: implement memory protection optionsMax Filippov1-1/+55
2011-09-10target-xtensa: add gdb supportMax Filippov1-0/+14
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov1-0/+2
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov1-0/+2
2011-09-10target-xtensa: implement interrupt optionMax Filippov1-1/+44
2011-09-10target-xtensa: implement extended L32RMax Filippov1-0/+6
2011-09-10target-xtensa: implement loop optionMax Filippov1-0/+3
2011-09-10target-xtensa: implement windowed registersMax Filippov1-0/+8
2011-09-10target-xtensa: implement exceptionsMax Filippov1-0/+67
2011-09-10target-xtensa: add PS register and access controlMax Filippov1-1/+52
2011-09-10target-xtensa: implement LSAI groupMax Filippov1-0/+1
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov1-0/+4
2011-09-10target-xtensa: add special and user registersMax Filippov1-0/+7
2011-09-10target-xtensa: implement disas_xtensa_insnMax Filippov1-0/+67
2011-09-10target-xtensa: add target stubsMax Filippov1-0/+95
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