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path: root/target-sparc/helper.c
AgeCommit message (Expand)AuthorFilesLines
2010-03-17Large page TLB flushPaul Brook1-14/+26
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-7/+1
2010-01-31sparc32 don't mark page dirty when failingArtyom Tarasenko1-5/+6
2010-01-17Sparc: improve CPU register dumpBlue Swirl1-30/+55
2010-01-13Sparc32: remove unused variable, spotted by clangBlue Swirl1-5/+0
2010-01-08sparc64: add PIL to cpu state dumpIgor V. Kovalenko1-0/+1
2009-12-05Sparc64: handle MMU global bit and nucleus contextBlue Swirl1-11/+19
2009-12-04Sparc64: fix compilation with DEBUG_MMUBlue Swirl1-15/+15
2009-11-07user: move CPU reset call to main.c for x86/PPC/SparcBlue Swirl1-3/+0
2009-11-07sparc32 (mostly): remove unneeded calls to device resetBlue Swirl1-0/+2
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-18/+18
2009-10-01Get rid of _t suffixmalc1-18/+18
2009-08-18Sparc32/64: Fix user emulator breakageBlue Swirl1-1/+1
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko1-2/+3
2009-07-27sparc64 really implement itlb/dtlb automatic replacement writesIgor Kovalenko1-1/+3
2009-07-27sparc64 name mmu registers and general cleanupIgor Kovalenko1-28/+40
2009-07-20Fix most warnings (errors with -Werror) when debugging is enabledBlue Swirl1-10/+10
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
2009-07-12sparc64: trap handling correctionsIgor Kovalenko1-0/+4
2009-07-12sparc64: unify mmu tag matching codeIgor Kovalenko1-44/+57
2009-07-12sparc64: mmu bypass mode correctionIgor Kovalenko1-3/+11
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
2009-05-10Use dynamical computation for condition codesBlue Swirl1-0/+1
2009-05-02Clarify: dmmuregs[1] is not a typoBlue Swirl1-0/+1
2009-04-28sparc64 fix context value for ITLB faultIgor Kovalenko1-1/+1
2009-04-27sparc64 fix TLB match codeIgor Kovalenko1-7/+7
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori1-0/+1
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir11-2/+3
2009-02-21Turn MMUs and caches off on resetblueswir11-0/+1
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-2/+0
2009-01-26Log reset events (Jan Kiszka)aliguori1-0/+5
2009-01-14Get rid of user_mode_onlyaurel321-1/+0
2009-01-12Fix TLB access (Jakub Jermar)blueswir11-10/+10
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel321-1/+1
2008-12-23Better SuperSPARC emulation (Robert Reif)blueswir11-23/+27
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-2/+2
2008-10-07Add static (spotted by sparse)blueswir11-1/+1
2008-10-03Rearrange tick functionsblueswir11-31/+0
2008-09-26Add a generic Niagara machineblueswir11-2/+1
2008-09-26Move also DEBUG_PCALL (see r5085)blueswir11-1/+0
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir11-1/+1
2008-08-29Fix Sparc64 boot on i386 host:blueswir11-242/+0
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir11-26/+10
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir11-41/+44
2008-07-22Add T1 and T2 CPUs, add a Sun4v machineblueswir11-0/+22
2008-07-21Use MMU globals for some MMU trapsblueswir11-3/+17
2008-07-21Fix reset vectorblueswir11-1/+1
2008-07-20Print default and available CPU features separatelyblueswir11-4/+7
2008-07-20Make UA200x features selectable, add MMU typesblueswir11-17/+22
2008-07-19Update TLB miss addressesblueswir11-0/+2
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