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2012-02-02PPC: E500: Implement msgsndAlexander Graf1-0/+16
This patch implements the msgsnd instruction. It is part of the Embedded.Processor Control specification and allows one CPU to IPI another CPU without going through an interrupt controller. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: E500: Implement msgclrAlexander Graf1-0/+18
This patch implements the msgclr instruction. It is part of the Embedded.Processor Control specification and clears pending doorbell interrupts on the current CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: Check for TLB overrunAlexander Graf1-0/+1
Our internal helpers to fetch TLB entries were not able to tell us that an entry doesn't even exist. Pass an error out if we hit such a case to not accidently pass beyond the TLB array. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: booke206: Implement tlbilxAlexander Graf1-0/+35
The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used to flush TLB entries. It's the recommended way of flushing in virtualized environments. So far we got away without implementing it, but Linux for e500mc uses this instruction, so we better add it :). Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: rename msync to msync_4xxAlexander Graf1-2/+2
The msync instruction as defined today is only valid on 4xx cores, not on e500 which also supports msync, but treats it the same way as sync. Rename it to reflect that it's 4xx only. Signed-off-by: Alexander Graf <agraf@suse.de>
2012-02-02PPC: e500: msync is 440 only, e500 has real syncAlexander Graf1-2/+1
The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-11-11PPC: Fix for the gdb single step problem on an rfi instructionSebastian Bauer1-1/+3
When using gdb to single step a ppc interrupt routine, the execution flow passes the rfi instruction without actually returning from the interrupt. The patch fixes this by avoiding to update the nip when the debug exception is raised and a previous POWERPC_EXCP_SYNC was set. The latter is the case only, if code for rfi or a related instruction was generated. Signed-off-by: Sebastian Bauer <mail@sebastianbauer.info> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-30Set an invalid-bits mask for each SPE instructionsFabien Chouteau1-229/+271
SPE instructions are defined by pairs. Currently, the invalid-bits mask is set for the first instruction, but the second one can have a different mask. example: GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-10-06Implement POWER7's CFAR in TCGDavid Gibson1-0/+28
This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-08-23PPC: E500: Inject SPE exception on invalid SPE accessAlexander Graf1-39/+39
When accessing an SPE instruction despite it being not available, throw an SPE exception instead of an APU exception. That way the guest knows what's going on and actually uses SPE. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-07-01Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl1-11/+6
* 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-17PPC: Only set lower 32bits with mtmsrAlexander Graf1-11/+6
As Nathan pointed out correctly, the mtmsr instruction does not modify the high 32 bits of MSR. It also doesn't matter if SF is set or not, the instruction always behaves the same. This patch moves it a bit closer to the spec. Reported-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-06-03target-ppc: remove old CONFIG_SOFTFLOAT #ifdefAurelien Jarno1-2/+0
target-ppc has been switched to softfloat only long ago, but a few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them. Cc: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-05-12PPC: Implement e500 (FSL) MMUAlexander Graf1-5/+90
Most of the code to support e500 style MMUs is already in place, but we're missing on some of the special TLB0-TLB1 handling code and slightly different TLB modification. This patch adds support for the FSL style MMU. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-12PPC: Add another 64 bits to instruction feature maskAlexander Graf1-6/+19
To enable quick runtime detection of instruction groups to the currently selected CPU emulation, we have a feature mask of what exactly the respective instruction supports. This feature mask is 64 bits long and we just successfully exceeded those 64 bits. To add more features, we need to think of something. The easiest solution that came to my mind was to simply add another 64 bits that we can also match on. Since the comparison is only done on start of the qemu process to generate an internal opcode calling table, we should be fine on any performance penalties here. Signed-off-by: Alexander Graf <agraf@suse.de>
2011-05-09monitor: add PPC BookE SPRsScott Wood1-3/+79
Read them via KVM_GET_SREGS in kvm_arch_get_registers(), and display them in "info registers". Also get CR and PID from the existing KVM_GET_REGS. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-20Remove unused function parameters from gen_pc_load and rename the functionStefan Weil1-2/+1
Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-10Fix conversions from pointer to tcg_target_longStefan Weil1-1/+1
tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-01Parse SDR1 on mtspr instead of at translate timeDavid Gibson1-1/+1
On ppc machines with hash table MMUs, the special purpose register SDR1 contains both the base address of the encoded size (hashed) page tables. At present, we interpret the SDR1 value within the address translation path. But because the encodings of the size for 32-bit and 64-bit are different this makes for a confusing branch on the MMU type with a bunch of curly shifts and masks in the middle of the translate path. This patch cleans things up by moving the interpretation on SDR1 into the helper function handling the write to the register. This leaves a simple pre-sanitized base address and mask for the hash table in the CPUState structure which is easier to work with in the translation path. This makes the translation path more readable. It addresses the FIXME comment currently in the mtsdr1 helper, by validating the SDR1 value during interpretation. Finally it opens the way for emulating a pSeries-style partition where the hash table used for translation is not mapped into the guests's RAM. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Correct ppc popcntb logic, implement popcntw and popcntdDavid Gibson1-5/+15
qemu already includes support for the popcntb instruction introduced in POWER5 (although it doesn't actually allow you to choose POWER5). However, the logic is slightly incorrect: it will generate results truncated to 32-bits when the CPU is in 32-bit mode. This is not normal for powerpc - generally arithmetic instructions on a 64-bit powerpc cpu will generate full 64 bit results, it's just that only the low 32 bits will be significant for condition codes. This patch corrects this nit, which actually simplifies the code slightly. In addition, this patch implements the popcntw and popcntd instructions added in POWER7, in preparation for allowing POWER7 as an emulated CPU. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01Implement PowerPC slbmfee and slbmfev instructionsDavid Gibson1-1/+30
For a 64-bit PowerPC target, qemu correctly implements translation through the segment lookaside buffer. Likewise it supports the slbmte instruction which is used to load entries into the SLB. However, it does not emulate the slbmfee and slbmfev instructions which read SLB entries back into registers. Because these are only occasionally used in guests (mostly for debugging) we get away with it. However, given the recent SLB cleanups, it becomes quite easy to implement these, and thereby allow, amongst other things, a guest Linux to use xmon's command to dump the SLB. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-04-01target-ppc: ext32u instead of andi with constantAurelien Jarno1-4/+4
Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2011-03-22target-ppc: add support for 6 SPE instructionsFabien Chouteau1-4/+198
Add support for 6 SPE instructions: evmra, evmwsmi{a{a}}, evmwumi{a{a}} Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-21ppc: Correct BookE tlb readsEdgar E. Iglesias1-1/+1
Call the tlb read helper (and not the write helper) for tlb reads. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-12-31Fix translation of unary PPC/SPE instructions (efdneg etc.).Mike Pall1-18/+21
Signed-off-by: Mike Pall <mike-lp10@luajit.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-8/+6
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-09-15PPC: Enable hint bits for lwarx/ldarxAlexander Graf1-2/+2
The lwarx and ldarx instructions have a bit to give some hint to the CPU which is safe to ignore. We currently refuse to accept any instruction with that bit set, as it used to be declared MBZ. Let's remove the reserved bit and make the instruction work as expected. This fixes Linux boot for ppc64. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-07-13target-ppc: add vexptefp instructionAurelien Jarno1-0/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-22Fix %lld or %llx printf format useBlue Swirl1-3/+4
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-05target-ppc: Remove duplicate cpu log.Richard Henderson1-2/+0
Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-25ppc: remove dead assignments, spotted by clang analyzerBlue Swirl1-1/+1
Value stored is never read. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-04-18PPC: avoid function pointer type mismatch, spotted by clangBlue Swirl1-5/+3
Fixes clang errors: CC ppc-softmmu/translate.o /src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(read_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3748:28: note: instantiated from: if (likely(read_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(write_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3903:29: note: instantiated from: if (likely(write_cb != SPR_NOACCESS)) { Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-11target-ppc: fix evsrwu and evsrws (second try)Aurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11target-ppc: fix evsrwu and evsrwsAurelien Jarno1-2/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-11target-ppc: fix evslw instructionAurelien Jarno1-1/+1
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28target-ppc: don't print invalid opcode messages on the consoleAurelien Jarno1-11/+0
Invalid opcode messages can be perfectly normal, for example if this code is never executed. Don't print an error message on the console, but keep the message in the log for debugging purposes. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-28Revert "target-ppc: stop translation after a trap instruction"Aurelien Jarno1-12/+8
This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
2010-02-28target-ppc: stop translation after a trap instructionAurelien Jarno1-8/+12
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-27target-ppc: fix SPE evsplat* instructionsNathan Froyd1-2/+2
The shifts in the gen_evsplat* functions were expecting rA to be masked, not extracted, and so used the wrong shift amounts to sign-extend or pad with zeroes. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-9/+9
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-9/+9
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-09-28target-ppc: log instructions start in TCG codeAurelien Jarno1-0/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-25static and inline should came before the type of the functionsJuan Quintela1-4/+4
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-18target-ppc: optimize slw/srw/sld/srdAurelien Jarno1-49/+49
Remove a temp local variable and a jump by computing a mask with shifts. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-12Fix sys-queue.h conflict for goodBlue Swirl1-2/+2
Problem: Our file sys-queue.h is a copy of the BSD file, but there are some additions and it's not entirely compatible. Because of that, there have been conflicts with system headers on BSD systems. Some hacks have been introduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896, f40d753718c72693c5f520f0d9899f6e50395e94, 96555a96d724016e13190b28cffa3bc929ac60dc and 3990d09adf4463eca200ad964cc55643c33feb50 but the fixes were fragile. Solution: Avoid the conflict entirely by renaming the functions and the file. Revert the previous hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16Replace REGX with PRIx64Blue Swirl1-1/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plxBlue Swirl1-27/+31
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-16Replace always_inline with inlineBlue Swirl1-156/+162
We define inline as always_inline. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-03target-ppc: add exceptions for conditional storesNathan Froyd1-20/+51
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
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