diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2009-09-30 23:09:35 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2009-10-04 13:24:45 +0200 |
| commit | cfc86988a830d89ed22433af83711847d7859b15 (patch) | |
| tree | db11df76590d6e22d9c934d99adb129c811344f2 /tcg/tcg-opc.h | |
| parent | 3bc0bdcaadef1100ce2413af818d9c8e2f6319fc (diff) | |
tcg: add ext{8,16,32}u_i{32,64} TCG ops
Currently zero extensions ops are implemented by a and op with a
constant. This is then catched in some backend, and replaced by
a zero extension instruction. While this works well on RISC
machines, this adds a useless register move on non-RISC machines.
Example on x86:
ext16u_i32 r1, r2
is translated into
mov %eax,%ebx
movzwl %bx, %ebx
while the optimized version should be:
movzwl %ax, %ebx
This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be
implemented in the backends to avoid emitting useless register
moves.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/tcg-opc.h')
| -rw-r--r-- | tcg/tcg-opc.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index 3a095fce1..b7f3fd7e6 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -89,6 +89,12 @@ DEF2(ext8s_i32, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_ext16s_i32 DEF2(ext16s_i32, 1, 1, 0, 0) #endif +#ifdef TCG_TARGET_HAS_ext8u_i32 +DEF2(ext8u_i32, 1, 1, 0, 0) +#endif +#ifdef TCG_TARGET_HAS_ext16u_i32 +DEF2(ext16u_i32, 1, 1, 0, 0) +#endif #ifdef TCG_TARGET_HAS_bswap16_i32 DEF2(bswap16_i32, 1, 1, 0, 0) #endif @@ -152,6 +158,15 @@ DEF2(ext16s_i64, 1, 1, 0, 0) #ifdef TCG_TARGET_HAS_ext32s_i64 DEF2(ext32s_i64, 1, 1, 0, 0) #endif +#ifdef TCG_TARGET_HAS_ext8u_i64 +DEF2(ext8u_i64, 1, 1, 0, 0) +#endif +#ifdef TCG_TARGET_HAS_ext16u_i64 +DEF2(ext16u_i64, 1, 1, 0, 0) +#endif +#ifdef TCG_TARGET_HAS_ext32u_i64 +DEF2(ext32u_i64, 1, 1, 0, 0) +#endif #ifdef TCG_TARGET_HAS_bswap16_i64 DEF2(bswap16_i64, 1, 1, 0, 0) #endif |