diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-30 22:37:17 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-08-30 22:37:17 +0000 |
| commit | c047da1af40c116fb9b365ccaa3ae6dda80727d1 (patch) | |
| tree | 06b4a49e39b3c316446d7e3fb1c8453ab0ccab16 /target-sh4 | |
| parent | 390af821662c9d6af90b8914ec3efd0f8b255aef (diff) | |
SH4: Convert shift functions to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-sh4')
| -rw-r--r-- | target-sh4/op.c | 21 | ||||
| -rw-r--r-- | target-sh4/translate.c | 12 |
2 files changed, 9 insertions, 24 deletions
diff --git a/target-sh4/op.c b/target-sh4/op.c index 831307023..7bd2e18dc 100644 --- a/target-sh4/op.c +++ b/target-sh4/op.c @@ -115,27 +115,6 @@ void OPPROTO op_rotr_Rn(void) RETURN(); } -void OPPROTO op_shal_Rn(void) -{ - cond_t(env->gregs[PARAM1] & 0x80000000); - env->gregs[PARAM1] <<= 1; - RETURN(); -} - -void OPPROTO op_shar_Rn(void) -{ - cond_t(env->gregs[PARAM1] & 1); - *(int32_t *)&env->gregs[PARAM1] >>= 1; - RETURN(); -} - -void OPPROTO op_shlr_Rn(void) -{ - cond_t(env->gregs[PARAM1] & 1); - env->gregs[PARAM1] >>= 1; - RETURN(); -} - void OPPROTO op_fmov_frN_FT0(void) { FT0 = env->fregs[PARAM1]; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 985675bfa..6e29e8f9c 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1226,13 +1226,19 @@ void _decode_opc(DisasContext * ctx) return; case 0x4000: /* shll Rn */ case 0x4020: /* shal Rn */ - gen_op_shal_Rn(REG(B11_8)); + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 0x80000000); + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); + tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); return; case 0x4021: /* shar Rn */ - gen_op_shar_Rn(REG(B11_8)); + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); + tcg_gen_sari_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); return; case 0x4001: /* shlr Rn */ - gen_op_shlr_Rn(REG(B11_8)); + tcg_gen_andi_i32(cpu_T[0], cpu_gregs[REG(B11_8)], 1); + gen_cmp_imm(TCG_COND_NE, cpu_T[0], 0); + tcg_gen_shri_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 1); return; case 0x4008: /* shll2 Rn */ tcg_gen_shli_i32(cpu_gregs[REG(B11_8)], cpu_gregs[REG(B11_8)], 2); |