diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-15 21:26:37 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-04-15 21:26:37 +0000 |
| commit | 171b31e7c7b771dc9e20fcb8305fc330ee59c7a6 (patch) | |
| tree | c5dcf9876370f9221c47a7c1f0455bb3751a5748 /target-mips/translate.c | |
| parent | 80c27194a7be757ef5a9cec978d1d8faaa4cee81 (diff) | |
Don't use T2 for INS, it conflicts with branch delay slot handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2674 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-mips/translate.c')
| -rw-r--r-- | target-mips/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 59868f695..00ca4e21c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1722,25 +1722,25 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, case OPC_INS: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T2, rt); + GEN_LOAD_REG_TN(T0, rt); gen_op_ins(lsb, msb - lsb + 1); break; case OPC_DINSM: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T2, rt); + GEN_LOAD_REG_TN(T0, rt); gen_op_ins(lsb, msb - lsb + 1 + 32); break; case OPC_DINSU: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T2, rt); + GEN_LOAD_REG_TN(T0, rt); gen_op_ins(lsb + 32, msb - lsb + 1); break; case OPC_DINS: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T2, rt); + GEN_LOAD_REG_TN(T0, rt); gen_op_ins(lsb, msb - lsb + 1); break; default: |