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path: root/src/host/trxcon/trx_if.h
AgeCommit message (Expand)AuthorFilesLines
2019-01-17trxcon/trx_if: refactor trx_if_open()Vadim Yanitskiy1-2/+2
2018-11-29trxcon/trx_if.c: add SETFH CTRL command supportVadim Yanitskiy1-0/+2
2018-09-07trxcon/trx_if.c: drop unused SETPOWER and ADJPOWERVadim Yanitskiy1-3/+0
2018-09-06trxcon: avoid arfcn / band_arfcn naming confusionVadim Yanitskiy1-5/+5
2018-03-01trxcon: Fix '-i' to specify the "TRX IP address"Harald Welte1-1/+2
2017-12-05host/trxcon: forward Timing Advance value to transceiverVadim Yanitskiy1-0/+2
2017-12-04host/trxcon/trx_if.c: get rid of useless commandsVadim Yanitskiy1-3/+0
2017-11-19host/trxcon/scheduler: simplify timeslot managementVadim Yanitskiy1-1/+1
2017-11-19host/trxcon/l1ctl.c: handle L1CTL_PARAM_REQVadim Yanitskiy1-0/+2
2017-11-19host/trxcon/trx_if.c: get rid of CLCK interfaceVadim Yanitskiy1-1/+0
2017-11-19host/trxcon/scheduler: implement TSC selectionVadim Yanitskiy1-1/+1
2017-11-19host/trxcon/l1ctl.c: handle L1CTL_DM_{EST,REL}_REQVadim Yanitskiy1-0/+1
2017-11-19host/trxcon/trx_if.c: add power measurement commandVadim Yanitskiy1-0/+5
2017-11-19host/trxcon/scheduler: store BSIC in trx_instanceVadim Yanitskiy1-0/+3
2017-11-19host/trxcon/trx_if.c: expose the trx_if_tx_burst()Vadim Yanitskiy1-0/+3
2017-11-19host/trxcon: bind L1CTL link with TRX and vice versaVadim Yanitskiy1-0/+6
2017-11-19host/trxcon: store arfcn and band in trx_instanceVadim Yanitskiy1-0/+1
2017-11-19host/trxcon/scheduler: implement management functionsVadim Yanitskiy1-0/+2
2017-11-19host/trxcon/trx_if.c: handle clock indicationsVadim Yanitskiy1-0/+5
2017-11-19host/trxcon: integrate osmo-fsm frameworkVadim Yanitskiy1-0/+12
2017-11-19host/trxcon/trx_if.c: add ECHO commandVadim Yanitskiy1-0/+1
2017-11-19host/trxcon: initial release of transceiver interfaceVadim Yanitskiy1-0/+38
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