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| author | Vadim Yanitskiy <axilirator@gmail.com> | 2017-07-16 17:15:56 +0700 |
|---|---|---|
| committer | Vadim Yanitskiy <axilirator@gmail.com> | 2017-11-19 17:35:07 +0700 |
| commit | 77b6833146618d119642c1fc61779ca96bf6e99c (patch) | |
| tree | ced4c43832f16830147fb98393bb096aec7ecea6 /src | |
| parent | f2af7d2953429a15cda5b52bedec226ea0b47aab (diff) | |
host/trxcon/scheduler: add a reference to GSM 05.02
Change-Id: I067af9c114bcbc5bd74515d5008e21a07fd0167e
Diffstat (limited to 'src')
| -rw-r--r-- | src/host/trxcon/sched_lchan_handlers.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/host/trxcon/sched_lchan_handlers.c b/src/host/trxcon/sched_lchan_handlers.c index 1c7a3136..fcc4e71c 100644 --- a/src/host/trxcon/sched_lchan_handlers.c +++ b/src/host/trxcon/sched_lchan_handlers.c @@ -395,7 +395,10 @@ int rx_sch_fn(struct trx_instance *trx, struct trx_ts *ts, return 0; } -/* 41-bit RACH synchronization sequence */ +/** + * 41-bit RACH synchronization sequence + * GSM 05.02 Chapter 5.2.7 Access burst (AB) + */ static ubit_t rach_synch_seq[] = { 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, |