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| author | Vadim Yanitskiy <axilirator@gmail.com> | 2018-03-22 23:04:16 +0700 |
|---|---|---|
| committer | Vadim Yanitskiy <axilirator@gmail.com> | 2018-03-22 23:04:16 +0700 |
| commit | 96a8f288c66dee920f5705dd976f13593fc29104 (patch) | |
| tree | 79aa667ed2b0a0242c7654e766221b7b6683c934 | |
| parent | e05f6901025cde493164d3cb016e4836749aebac (diff) | |
trxcon/scheduler: add CHAN_IS_SACCH macro
Change-Id: I2fc90d4732433f221c628058c9812815edf9c8cb
| -rw-r--r-- | src/host/trxcon/sched_trx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/host/trxcon/sched_trx.h b/src/host/trxcon/sched_trx.h index bba8bcf8..ce1c7f4f 100644 --- a/src/host/trxcon/sched_trx.h +++ b/src/host/trxcon/sched_trx.h @@ -292,6 +292,9 @@ int sched_prim_push(struct trx_instance *trx, #define CHAN_IS_TCH(chan) \ (chan == TRXC_TCHF || chan == TRXC_TCHH_0 || chan == TRXC_TCHH_1) +#define CHAN_IS_SACCH(chan) \ + (trx_lchan_desc[chan].link_id & TRX_CH_LID_SACCH) + #define PRIM_IS_TCH(prim) \ CHAN_IS_TCH(prim->chan) && prim->payload_len != GSM_MACBLOCK_LEN |