diff options
author | Andreas.Eversberg <jolly@eversberg.eu> | 2010-10-30 17:27:03 +0200 |
---|---|---|
committer | Sylvain Munaut <tnt@246tNt.com> | 2010-10-30 17:31:09 +0200 |
commit | 072d7dd4bfef5bad171d0561a6ce4f984a26fd88 (patch) | |
tree | d3db75cebc547a03e4ee9502d94bcd571f6da32f | |
parent | 33ad399e21e9d5b4867e229a79f8f60bcf8908f2 (diff) |
target/fw/layer1: Change L1CTL RACH req to properly use all slots
Written-by: Andreas Eversberg <jolly@eversberg.eu>
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
-rw-r--r-- | include/l1ctl_proto.h | 5 | ||||
-rw-r--r-- | src/target/firmware/include/layer1/async.h | 4 | ||||
-rw-r--r-- | src/target/firmware/include/layer1/prim.h | 2 | ||||
-rw-r--r-- | src/target/firmware/layer1/l23_api.c | 6 | ||||
-rw-r--r-- | src/target/firmware/layer1/prim_rach.c | 32 |
5 files changed, 36 insertions, 13 deletions
diff --git a/include/l1ctl_proto.h b/include/l1ctl_proto.h index 24cb64ba..9adadfd1 100644 --- a/include/l1ctl_proto.h +++ b/include/l1ctl_proto.h @@ -176,9 +176,8 @@ struct l1ctl_tch_mode_req { /* the l1_info_ul header is in front */ struct l1ctl_rach_req { uint8_t ra; - uint8_t fn51; - uint8_t mf_off; - uint8_t padding[1]; + uint8_t combined; + uint16_t offset; } __attribute__((packed)); /* the l1_info_ul header is in front */ diff --git a/src/target/firmware/include/layer1/async.h b/src/target/firmware/include/layer1/async.h index f4d0b5a9..f8d6b716 100644 --- a/src/target/firmware/include/layer1/async.h +++ b/src/target/firmware/include/layer1/async.h @@ -29,8 +29,8 @@ void l1a_meas_msgb_set(struct msgb *msg); /* flush all pending msgb */ void l1a_txq_msgb_flush(struct llist_head *queue); -/* request a RACH request at the next multiframe T3 = fn51 */ -void l1a_rach_req(uint8_t fn51, uint8_t mf_off, uint8_t ra); +/* request a RACH */ +void l1a_rach_req(uint16_t offset, uint8_t combined, uint8_t ra); /* schedule frequency change */ void l1a_freq_req(uint32_t fn_sched); diff --git a/src/target/firmware/include/layer1/prim.h b/src/target/firmware/include/layer1/prim.h index c8e49a66..6ff40c92 100644 --- a/src/target/firmware/include/layer1/prim.h +++ b/src/target/firmware/include/layer1/prim.h @@ -20,7 +20,7 @@ void l1s_nb_test(uint8_t base_fn); void l1s_fbsb_req(uint8_t base_fn, struct l1ctl_fbsb_req *req); void l1a_freq_req(uint32_t fn_sched); -void l1a_rach_req(uint8_t fn51, uint8_t mf_off, uint8_t ra); +void l1a_rach_req(uint16_t offset, uint8_t combined, uint8_t ra); /* Primitives raw scheduling sets */ extern const struct tdma_sched_item nb_sched_set[]; diff --git a/src/target/firmware/layer1/l23_api.c b/src/target/firmware/layer1/l23_api.c index e51dd5d6..19838f15 100644 --- a/src/target/firmware/layer1/l23_api.c +++ b/src/target/firmware/layer1/l23_api.c @@ -300,9 +300,11 @@ static void l1ctl_rx_rach_req(struct msgb *msg) struct l1ctl_info_ul *ul = (struct l1ctl_info_ul *) l1h->data; struct l1ctl_rach_req *rach_req = (struct l1ctl_rach_req *) ul->payload; - printd("L1CTL_RACH_REQ (ra=0x%02x, fn51=%d, mf_off=%d)\n", rach_req->ra, rach_req->fn51, rach_req->mf_off); + printd("L1CTL_RACH_REQ (ra=0x%02x, offset=%d combined=%d)\n", + rach_req->ra, ntohs(rach_req->offset), rach_req->combined); - l1a_rach_req(rach_req->fn51, rach_req->mf_off, rach_req->ra); + l1a_rach_req(ntohs(rach_req->offset), rach_req->combined, + rach_req->ra); } /* receive a L1CTL_DATA_REQ from L23 */ diff --git a/src/target/firmware/layer1/prim_rach.c b/src/target/firmware/layer1/prim_rach.c index 56cde49b..b0e7288d 100644 --- a/src/target/firmware/layer1/prim_rach.c +++ b/src/target/firmware/layer1/prim_rach.c @@ -113,18 +113,40 @@ static void l1a_rach_compl(__unused enum l1_compl c) l1_queue_for_l2(msg); } +static uint8_t t3_to_rach_comb[51] = { + 0, 0, 0, 0, + 0, 1, + 2, 2, 2, 2, 2, 2, 2, 2, + 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, + 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 25, 25, 25, 25, 25, 25, 25, + 25, 26, + 27, 27, 27, 27}; +static uint8_t rach_to_t3_comb[27] = { + 4, 5, + 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, + 45, 46}; + /* request a RACH request at the next multiframe T3 = fn51 */ -void l1a_rach_req(uint8_t fn51, uint8_t mf_off, uint8_t ra) +void l1a_rach_req(uint16_t offset, uint8_t combined, uint8_t ra) { uint32_t fn_sched; unsigned long flags; + offset += 3; + local_firq_save(flags); + if (combined) { + /* add elapsed RACH slots to offset */ + offset += t3_to_rach_comb[l1s.current_time.t3]; + /* offset is the number of RACH slots in the future */ + fn_sched = l1s.current_time.fn - l1s.current_time.t3; + fn_sched += offset / 27 * 51; + fn_sched += rach_to_t3_comb[offset % 27]; + } else + fn_sched = l1s.current_time.fn + offset; l1s.rach.ra = ra; - /* TODO: can we wrap here? I don't think so */ - fn_sched = l1s.current_time.fn - l1s.current_time.t3; - fn_sched += mf_off * 51; - fn_sched += fn51; sched_gsmtime(rach_sched_set_ul, fn_sched, 0); local_irq_restore(flags); |