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<?xml version="1.0"?>
<testsuite name='Titan' tests='117' failures='5' errors='0' skipped='0' inconc='0' time='MASKED'>
<testcase classname='PCU_Tests' name='TC_pcuif_suspend' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_suspend_active_tbf' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ta_ptcch_idle' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ta_rach_imm_ass' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ta_ul_ack_nack_first_block' time='MASKED'>
<failure type='fail-verdict'>Timing Advance mismatch: expected 2, but received 0
PCU_Tests.ttcn:MASKED PCU_Tests control part
PCU_Tests.ttcn:MASKED TC_ta_ul_ack_nack_first_block testcase
</failure>
</testcase>
<testcase classname='PCU_Tests' name='TC_ta_idle_dl_tbf_ass' time='MASKED'>
<failure type='fail-verdict'>Timing Advance value doesn't match
PCU_Tests.ttcn:MASKED PCU_Tests control part
PCU_Tests.ttcn:MASKED TC_ta_idle_dl_tbf_ass testcase
</failure>
</testcase>
<testcase classname='PCU_Tests' name='TC_ta_ptcch_ul_multi_tbf' time='MASKED'>
<failure type='fail-verdict'>Failed to match Timing Advance Index for #0
PCU_Tests.ttcn:MASKED PCU_Tests control part
PCU_Tests.ttcn:MASKED TC_ta_ptcch_ul_multi_tbf testcase
</failure>
</testcase>
<testcase classname='PCU_Tests' name='TC_cs_lqual_ul_tbf' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_cs_initial_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_cs_max_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_cs_initial_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_cs_max_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_cs1_to_cs4' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mcs_initial_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mcs_max_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mcs_initial_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mcs_max_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_t3141' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_n3101_max_t3169' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_n3103_max_t3169' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_x2031_t3191' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_zero_x2031_t3191' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_t3193' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_n3105_max_t3195' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_t3172_wait_ind_size0' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_t3172_wait_ind_size1' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_countdown_procedure' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_all_sizes' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_data_toolong_fills_padding' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mo_ping_pong' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mo_ping_pong_with_ul_racap' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_force_two_phase_access' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mt_ping_pong' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mt_ping_pong_with_dl_racap' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_intermediate_retrans' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_imm_ass_dl_block_retrans' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_flow_more_blocks' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_flow_multiple_llc_blocks' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_no_ack_retrans_imm_ass' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_llc_sapi_priority' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_bsn_wraparound_gprs' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_from_bts' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_from_sgsn_sign_ptmsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_from_sgsn_sign' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_from_sgsn_ptp' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_ps_from_sgsn_sign_ptmsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_ps_from_sgsn_sign' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_ps_from_sgsn_ptp' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_pch_timeout' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_multi_ms_imsi_tmsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_multi_ms_imsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_paging_cs_multi_ms_tmsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_bssgp_dl_unitdata_with_valid_imsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_bssgp_dl_unitdata_with_invalid_imsi' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_gprs_data_no_llc_ui_dummy' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_egprs_data_no_llc_ui_dummy' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_finished_pkt_dl_ass_pch' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_1phase_while_dl_ass_pch' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_2phase_while_dl_ass_pch' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_signalling' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_one_phase' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_two_phase' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_reject_content' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_reject_emergency' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_egprs_pkt_chan_req_reject_exhaustion' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_mo_ping_pong_with_ul_racap_egprs_only' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_fh_imm_ass_ul_egprs' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_fh_imm_ass_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_fh_imm_ass_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_fh_pkt_ass_ul' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_fh_pkt_ass_dl' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_multitrx_multims_alloc' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_dl_multislot_tbf_ms_class_from_sgsn' time='MASKED'>
<failure type='fail-verdict'>Expected 8 PDCH slots allocated but got 4
PCU_Tests.ttcn:MASKED PCU_Tests control part
PCU_Tests.ttcn:MASKED TC_dl_multislot_tbf_ms_class_from_sgsn testcase
</failure>
</testcase>
<testcase classname='PCU_Tests' name='TC_dl_multislot_tbf_ms_class_unknown' time='MASKED'>
<failure type='fail-verdict'>Expected 1 PDCH slots allocated but got 4
PCU_Tests.ttcn:MASKED PCU_Tests control part
PCU_Tests.ttcn:MASKED TC_dl_multislot_tbf_ms_class_unknown testcase
</failure>
</testcase>
<testcase classname='PCU_Tests' name='TC_dl_multislot_tbf_ms_class_from_2phase' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_multislot_tbf_ms_class_from_2phase' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_reestablish_with_pkt_resource_req' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_reestablish_with_pkt_resource_req_t3168' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_reestablish_with_pkt_dl_ack_nack' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ul_tbf_reestablish_with_pkt_dl_ack_nack_egprs' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_multiplex_dl_gprs_egprs' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pcuif_info_ind_subsequent' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_success' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_success_utran' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_success_eutran' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_success_no_ctrl_ack' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_success_twice' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_success_twice_nocache' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_rac_ci_resolve_timeout' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_si_resolve_timeout' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_dup' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_dup2' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_dup3' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_dup4' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_dup5' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_twice' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_twice2' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_twice3' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_twice4' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_twice5' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_nacc_outbound_pkt_cell_chg_notif_unassigned_dl_tbf' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_rim_ran_info_req_single_rep' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_rim_ran_info_req_single_rep_eutran' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_rim_ran_info_req_single_rep_no_si' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_pdch_energy_saving' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_stat_pdch_avail_occ' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_stat_pdch_avail_occ_ms_not_known_gprs' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_stat_pdch_avail_occ_ms_not_known_egprs' time='MASKED'/>
<testcase classname='PCU_Tests' name='TC_ratectr_all_available_allocated' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_reset' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_reset_retrans' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_alive' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_alive_timeout_reset' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_unblock' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_unblock_retrans' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_full_bringup' time='MASKED'/>
<testcase classname='PCU_Tests_NS' name='TC_ns_so_block' time='MASKED'/>
</testsuite>
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