Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2019-06-19 | clock-generator: Move GND via to avoid overlap with N$15 | Harald Welte | 1 | -6/+6 | |
2019-06-19 | <osmo-clock-gen: add more TVS for exposed signals, clean up and finish | Martin Schramm | 2 | -536/+1391 | |
2019-06-19 | osmo-clock-gen: capacitive coupling for XA input needed - added 100n | Martin Schramm | 2 | -58/+101 | |
This was a remark by tnt, thanks. | |||||
2019-06-19 | clock-generator: compacting + place MTA100 header (solves OSM#4050) | Martin Schramm | 2 | -1208/+509 | |
2019-06-19 | clock-generator: changes adressing OSM#4050 | Martin Schramm | 2 | -1831/+2677 | |
A shouded UEXT would need much space; no room for an MTA100 yet... tbd | |||||
2019-06-19 | clock-generator: insert changes discussed so far for v2 | Martin Schramm | 2 | -4207/+7211 | |
* selectable VDDIO{1..4} for PLL: either 3V3 or ADJ (VOUT/DAC) * use SAMD21 instead of SAMD11 * bring some GPIO on pin header * use GCLK_IO4 (PA10) to feed XA of PLL | |||||
2019-06-19 | clock-generator: add tracking LDO, make PCB four layer | Martin Schramm | 2 | -634/+1045 | |
2019-06-19 | WIP: click-generator: Replace U3 (so far SAMD11) with SAMD21 | Harald Welte | 2 | -775/+696 | |
Closes: OS#3856 | |||||
2019-01-28 | clock-gen: Add BOM information + PDF exports of schematics | Harald Welte | 5 | -298/+3653 | |
2019-01-27 | clock-gen: Update gpio spreadsheet with all assignments | Harald Welte | 1 | -30/+73 | |
The assignments have been chosen to be nearly identical to the SAMD11-XPRO board. | |||||
2019-01-27 | clock-gen: Minor changes; final version as ordered | Harald Welte | 2 | -40/+52 | |
* move DC jack to extend beyond PCB edge into front panel * harmonize component variants (10n only 0402, 4.7u only 0805) * add "sysmocom" as manufacturer name (WEEE requirement) | |||||
2019-01-27 | clock-gen: Cosmetic changes | Harald Welte | 2 | -1118/+1177 | |
2019-01-27 | clock-gen: finish routing of PCB layout | Harald Welte | 4 | -442/+1596 | |
2019-01-26 | clock-gen: Connect EEPROM WP to GND to disable write-protect | Harald Welte | 2 | -0/+6 | |
2019-01-26 | clock-gen: Add SPI; UEXT header; mounting holes; do layout/routing | Harald Welte | 3 | -177/+1042 | |
2019-01-23 | clock-generator: Most of the layout | Harald Welte | 2 | -2093/+2770 | |
Traces are intended for dual-layer 1mm FR4 PCB with 35um copper. | |||||
2019-01-23 | clock-generator: More schematics work; initial placement/grouping | Harald Welte | 2 | -0/+2366 | |
* add I2C EEPROM * start board design file * group parts to their respective "main part" * define TC-2030 pinout | |||||
2019-01-21 | clock-generator: More work on schematics (USB, UART, ESD) | Harald Welte | 1 | -57/+868 | |
2019-01-16 | initial check-in of upcoming clock-generator board | Harald Welte | 9 | -0/+114422 | |