Age | Commit message (Collapse) | Author | Files | Lines | |
---|---|---|---|---|---|
2017-03-23 | mpcie-breakout: disable tPlace layer | Harald Welte | 1 | -1/+1 | |
2017-03-23 | mpcie-breakout: USB_VBUS second parallel via to reduce impedance | Harald Welte | 1 | -0/+4 | |
2017-03-23 | mpcie-breakout: Digikey part numbers for U.FL and SMA | Harald Welte | 2 | -17/+198 | |
2017-03-23 | mcie-breakout: Align bLabels, more vias, cosmetics | Harald Welte | 2 | -28/+129 | |
2017-03-23 | mpcie-breakout: Add third U.FL-SMA group | Harald Welte | 2 | -24/+75 | |
2017-03-23 | mpcie-breakout: Enlarge to 70x70mm, add SMA, U.FL and Mounting Holes | Harald Welte | 2 | -232/+589 | |
2016-12-05 | mv-uart: Fix 'board doesn't enumerate if JP4 is closed" issue | Harald Welte | 3 | -82/+22 | |
Make sure the LDO is always powered up, so the CP2105 internal and external !RESET pull-ups are towards an active VIO voltage, rather than one that is switched off by !SUSPEND and thus keeps the CP2105 in reset. Closes: #1870 (https://osmocom.org/issues/1870) | |||||
2016-11-25 | add PCBA photographs | Harald Welte | 4 | -0/+0 | |
2016-10-28 | mpcie-breakoud: Add pdf renderings of schematicsmv_uart-v1mpcie_breakout-v2 | Harald Welte | 2 | -0/+0 | |
2016-10-28 | add mnb/mt files for mv-uart and mpcie-breakout | Harald Welte | 3 | -0/+66 | |
2016-10-28 | mpcie-breakout: mark C4 as POPULATED=FALSE | Harald Welte | 3 | -6/+10 | |
2016-10-28 | mv-uart: Add schematics + placement as PDF | Harald Welte | 2 | -0/+0 | |
2016-10-28 | mv-uart: Add digikey attributes for various 2.54mm hedaers | Harald Welte | 3 | -61/+79 | |
2016-10-28 | add PCB panel images for mv-uart and mpcie-breakout | Harald Welte | 2 | -0/+0 | |
2016-10-27 | mpcie-breakout: Change '1' marker of JP4 and avoid silk-screen overlap | Harald Welte | 1 | -2/+5 | |
2016-10-27 | mpcie-breakout: fix DRC violations (clearance) | Harald Welte | 1 | -25/+28 | |
2016-10-27 | mpcie-breakout: Add series LED for LED_WWAN | Harald Welte | 2 | -18/+63 | |
2016-10-27 | mpcie-breakout: Fix R4 (0603, not 0201 part) | Harald Welte | 3 | -16/+16 | |
2016-10-27 | mpcie-breakout: change 100uF caps from 1210 to 1206, reducing height | Harald Welte | 3 | -165/+262 | |
The current 100uF caps are too high at 2.9mm. They touch the shielding can of Quectel EC-20 modules, for exampel. Let's use 1206 packaged versions at 1.6mm instead. Also, add two more, for safety. | |||||
2016-10-27 | mv-uart: Use SP6T flash *without* OFF position | Harald Welte | 3 | -11/+11 | |
2016-10-10 | mpci-breakout: Add BOM attributes + export BOM | Harald Welte | 3 | -201/+598 | |
2016-10-10 | add .gitignore | Harald Welte | 1 | -0/+5 | |
2016-10-10 | Complete BOM attributes + export BOM | Harald Welte | 4 | -384/+838 | |
2016-10-09 | mpcie-breakout: Beautify schematics | Harald Welte | 1 | -707/+725 | |
2016-10-09 | mv-uart: Add PDF renderings | Harald Welte | 2 | -0/+0 | |
2016-10-09 | mv-uart: Beatify schematics + Add comments | Harald Welte | 1 | -678/+711 | |
2016-10-09 | mpcie-breakout: Add Digikey LINK for all major parts | Harald Welte | 2 | -50/+668 | |
2016-10-09 | mv-uart: Add digikey link for all major parts | Harald Welte | 2 | -81/+1213 | |
2016-10-08 | mv-uart: Add generated gerber files | Harald Welte | 12 | -0/+13830 | |
2016-10-08 | mv-uart: use Seeed Studio DRU | Harald Welte | 1 | -30/+34 | |
2016-10-08 | mv-uart: Add labels with name / copyright / license | Harald Welte | 1 | -3/+14 | |
2016-10-08 | mv-uart: align tNames labels in non-overlapping fashion | Harald Welte | 1 | -45/+153 | |
2016-10-08 | mpcie-breakout: add rendered gerber files | Harald Welte | 12 | -0/+27996 | |
2016-10-08 | mpcie-breakoud: Fix layer of JP4 label on silk-screen | Harald Welte | 1 | -1/+1 | |
2016-10-08 | initial import of new mpcie breakout board project | Harald Welte | 3 | -0/+16694 | |
2016-10-08 | move all mv-uart files to sub-directory | Harald Welte | 6 | -0/+0 | |
2016-10-07 | first fully routed version of mv-uart | Harald Welte | 2 | -84/+234 | |
2016-10-07 | WIP: design for a multi-voltage USB UART | Harald Welte | 6 | -0/+5220 | |
* an adjustible LDO with rotary switch is able to configure the UART voltage levels as needed. * alternatively, the UART logic level voltage (in the 1.8-3.3V range) can be provided by an external voltage reference. * TVS diodes protect the USB and UART sides from overvoltage and ESD * all voltages are available on a header to supply external circuitry * five GPIO pins are available on a header |