diff options
| author | Harald Welte <laforge@osmocom.org> | 2020-03-01 19:41:00 +0100 |
|---|---|---|
| committer | Harald Welte <laforge@osmocom.org> | 2020-03-01 19:42:20 +0100 |
| commit | 617288296fc07df28753944d9299e00a7cd9b931 (patch) | |
| tree | 55a52d49cf3a3f1a37cacd36536b8bbe1b4671fe | |
| parent | 7d09b416a29157df0064710e3440d4f511799677 (diff) | |
clock-generator: Fix VDD connection of TC2050 SWD connector
Closes: OS#4431
| -rw-r--r-- | clock-generator/clock-generator.brd | 9 | ||||
| -rw-r--r-- | clock-generator/clock-generator.sch | 12 |
2 files changed, 11 insertions, 10 deletions
diff --git a/clock-generator/clock-generator.brd b/clock-generator/clock-generator.brd index da1871b..1c11525 100644 --- a/clock-generator/clock-generator.brd +++ b/clock-generator/clock-generator.brd @@ -3679,6 +3679,12 @@ for the minimum (VIA) drill of 0.3mm as 0.36mm.</description> <wire x1="30.607" y1="75.1205" x2="30.48" y2="75.2475" width="0.3048" layer="1"/> <via x="30.48" y="75.2475" extent="1-16" drill="0.3"/> <wire x1="26.38425" y1="35.08375" x2="26.19375" y2="35.08375" width="0.3048" layer="1"/> +<contactref element="TC1" pad="4"/> +<wire x1="27.94" y1="84.7725" x2="27.6225" y2="84.455" width="0.3048" layer="1"/> +<wire x1="27.6225" y1="84.455" x2="27.6225" y2="83.82" width="0.3048" layer="1"/> +<via x="27.6225" y="83.82" extent="1-16" drill="0.3"/> +<wire x1="27.6225" y1="83.82" x2="27.305" y2="84.1375" width="0.3048" layer="15"/> +<wire x1="27.305" y1="84.1375" x2="27.305" y2="84.7725" width="0.3048" layer="15"/> </signal> <signal name="I2C_SDA"> <contactref element="U2" pad="5"/> @@ -4671,9 +4677,6 @@ for the minimum (VIA) drill of 0.3mm as 0.36mm.</description> <wire x1="27.6225" y1="44.6405" x2="27.6225" y2="43.48660625" width="0.3048" layer="1"/> <wire x1="27.6225" y1="43.48660625" x2="27.4955" y2="43.18" width="0.3048" layer="1" curve="-45"/> </signal> -<signal name="VDD_3V3" class="3"> -<contactref element="TC1" pad="4"/> -</signal> <signal name="N$8"> <contactref element="U2" pad="1"/> <contactref element="C11" pad="2"/> diff --git a/clock-generator/clock-generator.sch b/clock-generator/clock-generator.sch index d1009c8..cd7bdda 100644 --- a/clock-generator/clock-generator.sch +++ b/clock-generator/clock-generator.sch @@ -11510,6 +11510,11 @@ OSHW / CC-BY-SA</text> <pinref part="SUPPLY9" gate="VDD" pin="VDD"/> <wire x1="251.46" y1="43.18" x2="251.46" y2="40.64" width="0.1524" layer="91"/> </segment> +<segment> +<pinref part="TC1" gate="A" pin="4"/> +<wire x1="256.54" y1="127" x2="261.62" y2="127" width="0.1524" layer="91"/> +<label x="261.62" y="127" size="1.27" layer="95" xref="yes"/> +</segment> </net> <net name="!OEB" class="2"> <segment> @@ -11779,13 +11784,6 @@ OSHW / CC-BY-SA</text> <pinref part="D18" gate="D$1" pin="P$2"/> </segment> </net> -<net name="VDD_3V3" class="3"> -<segment> -<pinref part="TC1" gate="A" pin="4"/> -<wire x1="256.54" y1="127" x2="261.62" y2="127" width="0.1524" layer="91"/> -<label x="261.62" y="127" size="1.27" layer="95" xref="yes"/> -</segment> -</net> </nets> </sheet> </sheets> |