diff options
Diffstat (limited to 'fpga/hw-v2/Edfmap.ini')
| -rw-r--r-- | fpga/hw-v2/Edfmap.ini | 1340 |
1 files changed, 1340 insertions, 0 deletions
diff --git a/fpga/hw-v2/Edfmap.ini b/fpga/hw-v2/Edfmap.ini new file mode 100644 index 0000000..527585e --- /dev/null +++ b/fpga/hw-v2/Edfmap.ini @@ -0,0 +1,1340 @@ +
+[$GENERAL$]
+INIT=Z
+prefix=EDF_
+user_names=no
+edif2sdf_mapfile=
+logfile=efd2vhd.log
+
+[$EXPORT$]
+FMAP=NO
+HMAP=NO
+
+[$properties$]
+CYMODE=
+INIT=
+FD INIT=integer
+FDC INIT=integer
+FDCE INIT=integer
+FDCE_1 INIT=integer
+FDCP INIT=integer
+FDCPE INIT=integer
+FDCPE_1 INIT=integer
+FDCP_1 INIT=integer
+FDC_1 INIT=integer
+FDD INIT=integer
+FDDC INIT=integer
+FDDCE INIT=integer
+FDDCP INIT=integer
+FDDCPE INIT=integer
+FDDP INIT=integer
+FDDPE INIT=integer
+FDDRCPE INIT=integer
+FDDRRSE INIT=integer
+FDE INIT=integer
+FDE_1 INIT=integer
+FDP INIT=integer
+FDPE INIT=integer
+FDPE_1 INIT=integer
+FDP_1 INIT=integer
+FDR INIT=integer
+FDRE INIT=integer
+FDRE_1 INIT=integer
+FDRS INIT=integer
+FDRSE INIT=integer
+FDRSE_1 INIT=integer
+FDRS_1 INIT=integer
+FDR_1 INIT=integer
+FDS INIT=integer
+FDSE INIT=integer
+FDSE_1 INIT=integer
+FDS_1 INIT=integer
+FD_1 INIT=integer
+FJKC INIT=integer
+FJKCE INIT=integer
+FJKP INIT=integer
+FJKPE INIT=integer
+FJKRSE INIT=integer
+FJKSRE INIT=integer
+FTC INIT=integer
+FTCE INIT=integer
+FTCLE INIT=integer
+FTCLEX INIT=integer
+FTP INIT=integer
+FTPE INIT=integer
+FTPLE INIT=integer
+FTRSE INIT=integer
+FTRSLE INIT=integer
+FTSRE INIT=integer
+FTSRLE INIT=integer
+FTCP INIT=integer
+GTPA1_DUAL RXPRBSERR_LOOPBACK_0=integer
+GTPA1_DUAL RXPRBSERR_LOOPBACK_1=integer
+GTXE1 RXPRBSERR_LOOPBACK=integer
+IDDR INIT_Q1=integer
+IDDR INIT_Q2=integer
+IDDR2 INIT_Q0=integer
+IDDR2 INIT_Q1=integer
+IDDR_2CLK INIT_Q1=integer
+IDDR_2CLK INIT_Q2=integer
+IFD INIT=integer
+IFD_1 INIT=integer
+IFDI INIT=integer
+IFDI_1 INIT=integer
+IFDX INIT=integer
+IFDX_1 INIT=integer
+IFDXI INIT=integer
+IFDXI_1 INIT=integer
+ILD INIT=integer
+ILD_1 INIT=integer
+ILDI INIT=integer
+ILDI_1 INIT=integer
+ILDX INIT=integer
+ILDX_1 INIT=integer
+ILDXI INIT=integer
+ILDXI_1 INIT=integer
+ISERDES INIT_Q1=integer
+ISERDES INIT_Q2=integer
+ISERDES INIT_Q3=integer
+ISERDES INIT_Q4=integer
+ISERDES SRVAL_Q1=integer
+ISERDES SRVAL_Q2=integer
+ISERDES SRVAL_Q3=integer
+ISERDES SRVAL_Q4=integer
+ISERDES_NODELAY INIT_Q1=integer
+ISERDES_NODELAY INIT_Q2=integer
+ISERDES_NODELAY INIT_Q3=integer
+ISERDES_NODELAY INIT_Q4=integer
+ISERDES_NODELAY SRVAL_Q1=integer
+ISERDES_NODELAY SRVAL_Q2=integer
+ISERDES_NODELAY SRVAL_Q3=integer
+ISERDES_NODELAY SRVAL_Q4=integer
+LD INIT=integer
+LDC INIT=integer
+LDCE INIT=integer
+LDCE_1 INIT=integer
+LDCP INIT=integer
+LDCPE INIT=integer
+LDCPE_1 INIT=integer
+LDCP_1 INIT=integer
+LDC_1 INIT=integer
+LDE INIT=integer
+LDE_1 INIT=integer
+LDG INIT=integer
+LDP INIT=integer
+LDPE INIT=integer
+LDPE_1 INIT=integer
+LDP_1 INIT=integer
+LD_1 INIT=integer
+ODDR INIT=integer
+ODDR2 INIT=integer
+OFD INIT=integer
+OFD_1 INIT=integer
+OFDE INIT=integer
+OFDE_1 INIT=integer
+OFDI INIT=integer
+OFDI_1 INIT=integer
+OFDT INIT=integer
+OFDT_1 INIT=integer
+OFDX INIT=integer
+OFDX_1 INIT=integer
+OFDXI INIT=integer
+OFDXI_1 INIT=integer
+OSERDES INIT_OQ=integer
+OSERDES SRVAL_OQ=integer
+OSERDES INIT_TQ=integer
+OSERDES SRVAL_TQ=integer
+OSERDES INIT_OQ=integer
+OSERDES INIT_TQ=integer
+OSERDES SRVAL_OQ=integer
+OSERDES SRVAL_TQ=integer
+lut_function=
+eqn=
+INIT_00=
+INIT_01=
+INIT_02=
+INIT_03=
+INIT_04=
+INIT_05=
+INIT_06=
+INIT_07=
+INIT_08=
+INIT_09=
+INIT_0A=
+INIT_0B=
+INIT_0C=
+INIT_0D=
+INIT_0E=
+INIT_0F=
+
+INIT_10=
+INIT_11=
+INIT_12=
+INIT_13=
+INIT_14=
+INIT_15=
+INIT_16=
+INIT_17=
+INIT_18=
+INIT_19=
+INIT_1A=
+INIT_1B=
+INIT_1C=
+INIT_1D=
+INIT_1E=
+INIT_1F=
+
+INIT_20=
+INIT_21=
+INIT_22=
+INIT_23=
+INIT_24=
+INIT_25=
+INIT_26=
+INIT_27=
+INIT_28=
+INIT_29=
+INIT_2A=
+INIT_2B=
+INIT_2C=
+INIT_2D=
+INIT_2E=
+INIT_2F=
+
+INIT_30=
+INIT_31=
+INIT_32=
+INIT_33=
+INIT_34=
+INIT_35=
+INIT_36=
+INIT_37=
+INIT_38=
+INIT_39=
+INIT_3A=
+INIT_3B=
+INIT_3C=
+INIT_3D=
+INIT_3E=
+INIT_3F=
+
+INIT_40=
+INIT_41=
+INIT_42=
+INIT_43=
+INIT_44=
+INIT_45=
+INIT_46=
+INIT_47=
+INIT_48=
+INIT_49=
+INIT_4A=
+INIT_4B=
+INIT_4C=
+INIT_4D=
+INIT_4E=
+INIT_4F=
+
+INIT_50=
+INIT_51=
+INIT_52=
+INIT_53=
+INIT_54=
+INIT_55=
+INIT_56=
+INIT_57=
+INIT_58=
+INIT_59=
+INIT_5A=
+INIT_5B=
+INIT_5C=
+INIT_5D=
+INIT_5E=
+INIT_5F=
+
+INIT_60=
+INIT_61=
+INIT_62=
+INIT_63=
+INIT_64=
+INIT_65=
+INIT_66=
+INIT_67=
+INIT_68=
+INIT_69=
+INIT_6A=
+INIT_6B=
+INIT_6C=
+INIT_6D=
+INIT_6E=
+INIT_6F=
+
+INITP_00=
+INITP_01=
+INITP_02=
+INITP_03=
+INITP_04=
+INITP_05=
+INITP_06=
+INITP_07=
+
+LPM_TYPE=
+LPM_WIDTH=integer
+LPM_DIRECTION=
+P_WIDTH=
+P_OFFSET=
+CLKDV_DIVIDE=real
+DUTY_CYCLE_CORRECTION=bool
+WIDTH=integer
+DIVIDE1_BY=integer
+DIVIDE2_BY=integer
+TimingChecksOn=bool
+Xon=bool
+MsgOn=bool
+SEL_F500K=bool
+SEL_F16K=bool
+SEL_F490=bool
+SEL_F15=bool
+
+;added for virtex4 library
+CLKFX_DIVIDE=integer
+CLKFX_MULTIPLY=integer
+CLKIN_DIVIDE_BY_2=bool
+CLKIN_PERIOD=real
+CLKOUT_PHASE_SHIFT=
+CLK_FEEDBACK=
+DCM_PERFORMANCE_MODE=
+DESKEW_ADJUST=
+DFS_FREQUENCY_MODE=
+DLL_FREQUENCY_MODE=
+FACTORY_JF=
+STARTUP_WAIT=bool
+PHASE_SHIFT=integer
+MONITOR_MODE=
+SIM_MONITOR_FILE=
+JTAG_CHAIN=integer
+INIT_OUT=integer
+PRESELECT_I0=bool
+PRESELECT_I1=bool
+BUFR_DIVIDE=
+DSS_MODE=
+AREG=integer
+B_INPUT=
+BREG=integer
+CARRYINREG=integer
+CARRYINSELREG=integer
+CREG=integer
+LEGACY_MODE=
+MREG=integer
+OPMODEREG=integer
+PREG=integer
+SUBTRACTREG=integer
+ALMOST_FULL_OFFSET=
+ALMOST_EMPTY_OFFSET=
+DATA_WIDTH=integer
+FIRST_WORD_FALL_THROUGH=bool
+REFCLKSEL=
+SYNCLK1OUTEN=
+SYNCLK2OUTEN=
+CAPACITANCE=
+IOSTANDARD=
+DIFF_TERM=bool
+ICAP_WIDTH=
+DDR_CLK_EDGE=
+INIT_Q1=
+INIT_Q2=
+INIT_Q3=
+INIT_Q4=
+SRTYPE=
+IOBDELAY=
+IOBDELAY_TYPE=
+IOBDELAY_VALUE=integer
+DRIVE=integer
+SLEW=
+INIT_BITSLIPCNT=
+;INIT_CE= ;2 elems bit_vector
+;INIT_RANK1_PARTIAL= ;5 elems bit_vector
+;INIT_RANK2= ;6 elems bit_vector
+;INIT_RANK3= ;6 elems bit_vector
+BITSLIP_ENABLE=bool
+DATA_RATE=
+INTERFACE_TYPE=
+NUM_CE=integer
+SERDES_MODE=
+SRVAL_Q1=
+SRVAL_Q2=
+SRVAL_Q3=
+SRVAL_Q4=
+INIT_LOADCNT=
+SERDES_MODE=
+DATA_RATE_OQ=
+INIT_OQ=
+;INIT_ORANK1= ;6 elems bit_vector
+INIT_ORANK2_PARTIAL=
+DATA_RATE_TQ=
+TRISTATE_WIDTH=integer
+INIT_TQ=
+INIT_TRANK1=
+SRVAL_OQ=
+SRVAL_TQ=
+EN_REL=bool
+RST_DEASSERT_CLK=
+DOA_REG=integer
+DOB_REG=integer
+INIT_A=
+INIT_B=
+INVERT_CLK_DOA_REG=bool
+INVERT_CLK_DOB_REG=bool
+RAM_EXTENSION_A=
+RAM_EXTENSION_B=
+READ_WIDTH_A=integer
+READ_WIDTH_B=integer
+SIM_COLLISION_CHECK=
+SRVAL_A=
+SRVAL_B=
+WRITE_MODE_A=
+WRITE_MODE_B=
+WRITE_WIDTH_A=integer
+WRITE_WIDTH_B=integer
+SRVAL=
+WRITE_MODE=
+DISABLE_COLLISION_CHECK=bool
+ALIGN_COMMA_WORD=integer
+BANDGAPSEL=bool
+CCCB_ARBITRATOR_DISABLE=bool
+CHAN_BOND_LIMIT=integer
+CHAN_BOND_MODE=
+CHAN_BOND_ONE_SHOT=bool
+;CHAN_BOND_SEQ_1_1= ;11 elems bit_vector
+;CHAN_BOND_SEQ_1_2= ;11 elems bit_vector
+;CHAN_BOND_SEQ_1_3= ;11 elems bit_vector
+;CHAN_BOND_SEQ_1_4= ;11 elems bit_vector
+CHAN_BOND_SEQ_1_MASK=
+;CHAN_BOND_SEQ_2_1= ;11 elems bit_vector
+;CHAN_BOND_SEQ_2_2= ;11 elems bit_vector
+;CHAN_BOND_SEQ_2_3= ;11 elems bit_vector
+;CHAN_BOND_SEQ_2_4= ;11 elems bit_vector
+CHAN_BOND_SEQ_2_MASK=
+CHAN_BOND_SEQ_2_USE=bool
+CHAN_BOND_SEQ_LEN=integer
+CLK_CORRECT_USE=bool
+CLK_COR_8B10B_DE=bool
+CLK_COR_MAX_LAT=integer
+CLK_COR_MIN_LAT=integer
+;CLK_COR_SEQ_1_2= ;11 elems bit_vector
+;CLK_COR_SEQ_1_3= ;11 elems bit_vector
+;CLK_COR_SEQ_1_4= ;11 elems bit_vector
+CLK_COR_SEQ_1_MASK=
+;CLK_COR_SEQ_2_1= ;11 elems bit_vector
+;CLK_COR_SEQ_2_2= ;11 elems bit_vector
+;CLK_COR_SEQ_2_3= ;11 elems bit_vector
+;CLK_COR_SEQ_2_4= ;11 elems bit_vector
+CLK_COR_SEQ_2_MASK=
+CLK_COR_SEQ_2_USE=bool
+CLK_COR_SEQ_DROP=bool
+CLK_COR_SEQ_LEN=integer
+COMMA32=bool
+;COMMA_10B_MASK= ;10 elems bit_vector
+;CYCLE_LIMIT_SEL= ;2 elems bit_vector
+;DCDR_FILTER= ;3 elems bit_vector
+DEC_MCOMMA_DETECT=bool
+DEC_PCOMMA_DETECT=bool
+DEC_VALID_COMMA_ONLY=bool
+;DIGRX_FWDCLK= ;2 elems bit_vector
+DIGRX_SYNC_MODE=bool
+ENABLE_DCDR=bool
+;FDET_HYS_CAL= ;3 elems bit_vector
+;FDET_HYS_SEL= ;3 elems bit_vector
+;FDET_LCK_CAL= ;3 elems bit_vector
+;FDET_LCK_SEL= ;3 elems bit_vector
+;LOOPCAL_WAIT= ;2 elems bit_vector
+MCOMMA_32B_VALUE=
+MCOMMA_DETECT=bool
+OPPOSITE_SELECT=bool
+PCOMMA_32B_VALUE=
+PCOMMA_DETECT=bool
+PCS_BIT_SLIP=bool
+PMACLKENABLE=bool
+PMACOREPWRENABLE=bool
+PMA_BIT_SLIP=bool
+POWER_ENABLE=bool
+REPEATER=bool
+;RXAFEEQ= ;9 elems bit_vector
+;RXASYNCDIVIDE= ;2 elems bit_vector
+RXBY_32=bool
+;RXCDRLOS= ;6 elems bit_vector
+RXCLK0_FORCE_PMACLK=bool
+;RXCLKMODE= ;6 elems bit_vector
+RXCPSEL=bool
+RXCRCCLOCKDOUBLE=bool
+RXCRCENABLE=bool
+RXCRCINITVAL=
+RXCRCINVERTGEN=bool
+RXCRCSAMECLOCK=bool
+;RXCYCLE_LIMIT_SEL= ;2 elems bit_vector
+;RXDATA_SEL= ;2 elems bit_vector
+RXDCCOUPLE=bool
+RXDIGRESET=bool
+RXDIGRX=bool
+RXENABLE=bool
+RXEQ=
+RXFDCAL_CLOCK_DIVIDE=
+;RXFDET_HYS_CAL= ;3 elems bit_vector
+;RXFDET_HYS_SEL= ;3 elems bit_vector
+;RXFDET_LCK_CAL= ;3 elems bit_vector
+;RXFDET_LCK_SEL= ;3 elems bit_vector
+RXLB=bool
+;RXLKADJ= ;5 elems bit_vector
+;RXLOOPCAL_WAIT= ;2 elems bit_vector
+RXLOOPFILT=
+RXOUTDIV2SEL_A=
+RXOUTDIV2SEL_B=
+RXPD=bool
+RXPLLNDIVSEL=
+RXPMACLKSEL=
+;RXRCPADJ= ;3 elems bit_vector
+RXRECCLK1_USE_SYNC=bool
+;RXSLOWDOWN_CAL= ;2 elems bit_vector
+RXTADJ=bool
+RXUSRDIVISOR=integer
+;RXVCODAC_INIT= ;10 elems bit_vector
+RXVCO_CTRL_ENABLE=bool
+RX_BUFFER_USE=bool
+;RX_CLOCK_DIVIDER= ;2 elems bit_vector
+RX_LOS_INVALID_INCR=integer
+RX_LOS_THRESHOLD=integer
+SAMPLE_8X=bool
+SH_CNT_MAX=integer
+SH_INVALID_CNT_MAX=integer
+;SLOWDOWN_CAL= ;2 elems bit_vector
+TXABPMACLKSEL=
+;TXASYNCDIVIDE= ;2 elems bit_vector
+TXCLK0_FORCE_PMACLK=bool
+TXCLKMODE=
+TXCPSEL=bool
+TXCRCCLOCKDOUBLE=bool
+TXCRCENABLE=bool
+TXCRCINITVAL=
+TXCRCINVERTGEN=bool
+TXCRCSAMECLOCK=bool
+;TXDATA_SEL= ;2 elems bit_vector
+;TXDAT_PRDRV_DAC= ;3 elems bit_vector
+;TXDAT_TAP_DAC= ;5 elems bit_vector
+TXENABLE=bool
+TXFDCAL_CLOCK_DIVIDE=
+TXHIGHSIGNALEN=bool
+TXLOOPFILT=
+TXOUTCLK1_USE_SYNC=bool
+TXOUTDIV2SEL=
+TXPD=bool
+TXPHASESEL=bool
+TXPLLNDIVSEL=
+;TXPOST_PRDRV_DAC= ;3 elems bit_vector
+;TXPOST_TAP_DAC= ;5 elems bit_vector
+TXPOST_TAP_PD=bool
+;TXPRE_PRDRV_DAC= ;3 elems bit_vector
+;TXPRE_TAP_DAC= ;5 elems bit_vector
+TXPRE_TAP_PD=bool
+TXSLEWRATE=bool
+TXTERMTRIM=
+TX_BUFFER_USE=bool
+;TX_CLOCK_DIVIDER= ;2 elems bit_vector
+;VCODAC_INIT= ;10 elems bit_vector
+VCO_CTRL_ENABLE=bool
+
+
+;added for virtex5 library
+A_INPUT=
+ACASCREG=integer
+ALUMODEREG=integer
+AUTORESET_PATTERN_DETEC=boolean
+AUTORESET_PATTERN_DETECT_OPTINV=
+BANDWIDTH=
+BCASCREG=integer
+CLKFBOUT_MULT=integer
+CLKFBOUT_PHASE=real
+CLKIN1_PERIOD=real
+CLKIN2_PERIOD=real
+CLKOUT0_DIVIDE=integer
+CLKOUT0_DUTY_CYCLE=real
+CLKOUT0_PHASE=real
+CLKOUT1_DIVIDE=integer
+CLKOUT1_DUTY_CYCLE=real
+CLKOUT1_PHASE=real
+CLKOUT2_DIVIDE=integer
+CLKOUT2_DUTY_CYCLE=real
+CLKOUT2_PHASE=real
+CLKOUT3_DIVIDE=integer
+CLKOUT3_DUTY_CYCLE=real
+CLKOUT3_PHASE=real
+CLKOUT4_DIVIDE=integer
+CLKOUT4_DUTY_CYCLE=real
+CLKOUT4_PHASE=real
+CLKOUT5_DIVIDE=integer
+CLKOUT5_DUTY_CYCLE=real
+CLKOUT5_PHASE=real
+COMPENSATION=
+CRC_INIT=
+DELAY_SRC=
+DIVCLK_DIVIDE=integer
+DO_REG=integer
+EN_ECC_READ=boolean
+EN_ECC_SCRUB=boolean
+EN_ECC_WRITE=boolean
+EN_SYN=boolean
+IDELAY_TYPE=
+IDELAY_VALUE=integer
+INIT_70=
+INIT_71=
+INIT_72=
+INIT_73=
+INIT_74=
+INIT_75=
+INIT_76=
+INIT_77=
+INIT_78=
+INIT_79=
+INIT_7A=
+INIT_7B=
+INIT_7C=
+INIT_7D=
+INIT_7E=
+INIT_7F=
+INIT_C=
+INIT_D=
+INITP_08=
+INITP_09=
+INITP_0A=
+INITP_0B=
+INITP_0C=
+INITP_0D=
+INITP_0E=
+INITP_0F=
+MASK=
+MULTCARRYINREG=integer
+ODELAY_VALUE=integer
+PATTERN=
+PLL_PMCD_MODE=boolean
+POLYNOMIAL=
+REF_JITTER=real
+RESET_ON_LOSS_OF_LOCK=boolean
+SEL_MASK=
+SEL_PATTERN=
+SEL_ROUNDING_MASK=
+USE_MULT=
+USE_PATTERN_DETECT=
+USE_SIMD=
+;end of virtex5
+
+;added for virtex5 (ise9.1i sp2)
+CLKFBOUT_DESKEW_ADJUST=
+CLKOUT0_DESKEW_ADJUST=
+CLKOUT1_DESKEW_ADJUST=
+CLKOUT2_DESKEW_ADJUST=
+CLKOUT3_DESKEW_ADJUST=
+CLKOUT4_DESKEW_ADJUST=
+CLKOUT5_DESKEW_ADJUST=
+;end of virtex5 (ise9.1i sp2)
+
+;added for virtex5 (ise9.2i sp1)
+PCS_COM_CFG=
+SIGNAL_PATTERN=
+INIT_FILE=
+;end of virtex5 (ise9.2i sp1)
+
+;added for virtex5 (ise 10.1i)
+SIM_MODE=
+;end
+
+;added for spartan6, virtex6 (ise 11.2)
+A0REG=integer
+A1REG=integer
+AC_CAP_DIS_0=boolean
+AC_CAP_DIS_1=boolean
+ADREG=integer
+AUTORESET_PATDET=
+B0REG=integer
+B1REG=integer
+BUFFER_TYPE=
+BYPASS_GCLK_FF=boolean
+CARRYINSEL=
+CARRYOUTREG=integer
+CHAN_BOND_2_MAX_SKEW_0=integer
+CINVCTRL_SEL=boolean
+CLK_SEL_TYPE=
+CLKCM_CFG=boolean
+CLKFBOUT_MULT_F=real
+CLKFXDV_DIVIDE=integer
+CLKFX_MD_MAX=real
+CLKFBOUT_USE_FINE_PS=boolean
+CLKOUT0_DIVIDE_F=real
+CLKOUT0_USE_FINE_PS=boolean
+CLKOUT1_USE_FINE_PS=boolean
+CLKOUT2_USE_FINE_PS=boolean
+CLKOUT3_USE_FINE_PS=boolean
+CLKOUT4_CASCADE=boolean
+CLKOUT4_USE_FINE_PS=boolean
+CLKOUT5_USE_FINE_PS=boolean
+CLKOUT6_DIVIDE=integer
+CLKOUT6_DUTY_CYCLE=real
+CLKOUT6_PHASE=real
+CLKOUT6_USE_FINE_PS=boolean
+CLKRCV_TRST=boolean
+CLOCK_HOLD=boolean
+COUNTER_WRAPAROUND=
+DATA_RATE_OT=
+DDR3_DATA=integer
+DISABLE_JTAG=boolean
+DIVIDE_BYPASS=boolean
+DIVIDE=integer
+DFS_BANDWIDTH=
+DQSMASK_ENABLE=boolean
+DYN_CLK_INV_EN=boolean
+DYN_CLKDIV_INV_EN=boolean
+EN_RSTRAM_A=boolean
+EN_RSTRAM_B=boolean
+FARSRC=
+HIGH_PERFORMANCE_MODE=boolean
+I_INVERT=boolean
+IBUF_DELAY_VALUE=
+IBUF_LOW_PWR=boolean
+IDELAY2_VALUE=integer
+IDELAY_MODE=
+IFD_DELAY_VALUE=
+ISERDESE1 INIT_Q1=integer
+ISERDESE1 INIT_Q2=integer
+ISERDESE1 INIT_Q3=integer
+ISERDESE1 INIT_Q4=integer
+OSERDESE1 INIT_OQ=integer
+OSERDESE1 INIT_TQ=integer
+INMODEREG=integer
+InstancePath=
+ODELAY_TYPE=
+OFB_USED=boolean
+ONESHOT=boolean
+OUTPUT_MODE=
+PROG_MD_BANDWIDTH=
+PROG_USR=boolean
+RAM_MODE=
+REF_JITTER1=real
+REF_JITTER2=real
+REFCLK_FREQUENCY=real
+;REFCLKOUT_DLY= ;10 elems bit_vector
+RST_PRIORITY_A=
+RST_PRIORITY_B=
+RSTREG_PRIORITY_A=
+RSTREG_PRIORITY_B=
+RSTTYPE=
+SETUP_ALL=
+SIM_DEVICE=
+SIM_EFUSE_VALUE=
+SIM_TAPDELAY_VALUE=integer
+SPREAD_SPECTRUM=
+ISERDESE1 SRVAL_Q1=integer
+ISERDESE1 SRVAL_Q2=integer
+ISERDESE1 SRVAL_Q3=integer
+ISERDESE1 SRVAL_Q4=integer
+OSERDESE1 SRVAL_OQ=integer
+OSERDESE1 SRVAL_TQ=integer
+TRAIN_PATTERN=integer
+USE_DOUBLER=boolean
+USE_DPORT=boolean
+;end of spartan6, virtex6 (ise 11.2)
+
+; added for virtex6 (ise 11.3)
+TX_PMADATA_OPT=integer
+ENABLE_SYNC=bool
+;end of virtex6 (ise 11.3)
+
+[$LIBMAP$]
+work=.
+xilinx=xabelsim
+xilinxun=
+simprims=simprim
+DESIGNS=
+
+;FPGA Express
+VIRTEXE=VIRTEX
+COOLRUNNER=XC9500
+COOLRUNNER2=COOLRUNNERII
+SPARTAN2E=SPARTAN2E
+SPARTAN3=SPARTAN3
+SPARTAN3A=SPARTAN3A
+SPARTAN3E=SPARTAN3E
+SPARTANXL=SPARTANX
+XC3000A=XC3000
+XC3000L=XC3000
+XC3100A=XC3000
+XC3100L=XC3000
+XC4000EX=XC4000X
+XC4000L=XC4000E
+XC4000XL=XC4000X
+XC4000XLA=XC4000X
+XC4000XV=XC4000X
+XC9500XL=XC9500
+XC9500XV=XC9500
+
+;Synplify
+COOLRUNNERII=COOLRUNNERII
+Unilib=unisim
+XC4000=unisim
+XC5000=unisim
+
+;Exemplar
+xcv=unisim
+xcv2=unisim
+xcv2p=unisim
+xcve=unisim
+xi3=unisim
+xi31=unisim
+xi31a=unisim
+xi3a=unisim
+xi3l=unisim
+xi3t=unisim
+xi4=unisim
+xi4a=unisim
+xi4e=unisim
+xi4et=unisim
+xi4ex=unisim
+xi4h=unisim
+xi4l=unisim
+xi4t=unisim
+xi4xl=unisim
+xi4xla=unisim
+xi4xv=unisim
+xi5=unisim
+xi5t=unisim
+xi72a=unisim
+xi73=unisim
+xi7t=unisim
+xi95=unisim
+xi95xl=unisim
+xi95xv=unisim
+xis=unisim
+xis2=unisim
+xis2e=unisim
+xis3=unisim
+xisxl=unisim
+Active_lib=
+UnlinkedDesignLibrary=
+
+[$GSRGTS$]
+GSR=
+GR=
+GTS=
+PRLD=
+
+[$INCLUDE$]
+line1=library IEEE;
+line2=use IEEE.std_logic_1164.all;
+line3=library UNISIM;
+line4=use UNISIM.vcomponents.all;
+line5=library SIMPRIM;
+line6=use SIMPRIM.vcomponents.all;
+
+[TBUF]
+.=BUFT
+
+[VCC]
+VCC=P
+
+[GND]
+ground=G
+
+[X_FF]
+IN=I
+OUT=O
+
+;[OPAD]
+;OPAD=I
+;PAD=I
+
+;[IPAD]
+;IPAD=I
+;PAD=I
+
+;[IOPAD]
+;IOPAD=I
+;PAD=I
+
+[X_PU]
+OUT=O
+
+[X_LATCH]
+IN=I
+OUT=O
+
+[X_LATCHE]
+IN=I
+OUT=O
+
+[x_tri]
+IN=I
+OUT=O
+
+[x_buf]
+IN=I
+OUT=O
+
+[x_zero]
+OUT=O
+[x_one]
+OUT=O
+
+[x_and2]
+OUT=O
+IN1=I1
+IN0=I0
+
+[x_inv]
+IN=I
+OUT=O
+
+[x_or2]
+IN0=I0
+IN1=I1
+OUT=O
+
+[x_ckbuf]
+IN=I
+OUT=O
+
+[x_and3]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_and4]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+OUT=O
+
+[x_and5]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+OUT=O
+
+[x_and6]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+OUT=O
+
+[x_and7]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+OUT=O
+
+[x_and8]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+OUT=O
+
+[x_and16]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+OUT=O
+
+[x_or2]
+IN0=I0
+IN1=I1
+OUT=O
+
+[x_or3]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_or4]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+OUT=O
+
+[x_or5]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+OUT=O
+
+[x_or6]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+OUT=O
+
+[x_or7]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+OUT=O
+
+
+[x_or8]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+OUT=O
+
+[x_or16]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+OUT=O
+
+[x_xor2]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_xor3]
+IN0=I0
+IN1=I1
+IN2=I2
+OUT=O
+
+[x_xor4]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+OUT=O
+
+[x_xor5]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+OUT=O
+
+
+[x_lut2]
+OUT=O
+
+[x_lut3]
+OUT=O
+
+[x_lut4]
+OUT=O
+
+[x_RAM16]
+OUT=O
+IN=I
+
+[x_RAM32]
+OUT=O
+IN=I
+
+[x_RAMS16]
+OUT=O
+IN=I
+
+[x_RAMS32]
+OUT=O
+IN=I
+
+[x_RAMD16]
+OUT=O
+IN=I
+
+[x_RAMD32]
+OUT=O
+IN=I
+
+[x_MUX2]
+OUT=O
+INA=IA
+INB=IB
+
+[x_OR32]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+IN16=I16
+IN17=I17
+IN18=I18
+IN19=I19
+IN20=I20
+IN21=I21
+IN22=I22
+IN23=I23
+IN24=I24
+IN25=I25
+IN26=I26
+IN27=I27
+IN28=I28
+IN29=I29
+IN30=I30
+IN31=I31
+OUT=O
+
+[x_PD]
+OUT=O
+
+[x_XOR16]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+OUT=O
+
+[x_XOR32]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+IN16=I16
+IN17=I17
+IN18=I18
+IN19=I19
+IN20=I20
+IN21=I21
+IN22=I22
+IN23=I23
+IN24=I24
+IN25=I25
+IN26=I26
+IN27=I27
+IN28=I28
+IN29=I29
+IN30=I30
+IN31=I31
+OUT=O
+
+[x_AND32]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+IN8=I8
+IN9=I9
+IN10=I10
+IN11=I11
+IN12=I12
+IN13=I13
+IN14=I14
+IN15=I15
+IN16=I16
+IN17=I17
+IN18=I18
+IN19=I19
+IN20=I20
+IN21=I21
+IN22=I22
+IN23=I23
+IN24=I24
+IN25=I25
+IN26=I26
+IN27=I27
+IN28=I28
+IN29=I29
+IN30=I30
+IN31=I31
+OUT=O
+
+[x_XOR6]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+OUT=O
+
+[x_XOR7]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+OUT=O
+
+[x_XOR8]
+IN0=I0
+IN1=I1
+IN2=I2
+IN3=I3
+IN4=I4
+IN5=I5
+IN6=I6
+IN7=I7
+OUT=O
+
+[X_SFF]
+IN=I
+OUT=O
+
+[X_SUH]
+IN=I
+
+[FDCE]
+GSR=$HIDDEN$
+[FDPE]
+GSR=$HIDDEN$
+[IFDX]
+GSR=$HIDDEN$
+[IFDXI]
+GSR=$HIDDEN$
+[ILDX_1]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[ILDXI_1]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[ILFFX]
+GSR=$HIDDEN$
+[ILFFXI]
+GSR=$HIDDEN$
+[ILFLX_1]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[ILFLXI_1]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[LDCE_1]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[LDPE]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[LDPE_1]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[OAND2]
+GTS=$HIDDEN$
+[OBUF]
+GTS=$HIDDEN$
+[OBUFT]
+GTS=$HIDDEN$
+[OFDTX]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[OFDTXI]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[OFDX]
+GSR=$HIDDEN$
+GTS=$HIDDEN$
+[OFDXI]
+GTS=$HIDDEN$
+GSR=$HIDDEN$
+[OMUX2]
+GTS=$HIDDEN$
+[ONAND2]
+GTS=$HIDDEN$
+[ONOR2]
+GTS=$HIDDEN$
+[OOR2]
+GTS=$HIDDEN$
+[OXNOR2]
+GTS=$HIDDEN$
+[OXOR2]
+GTS=$HIDDEN$
|