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2020-09-04migrate to osmo-e1-hardware.gitHEADmasterHarald Welte58-129366/+0
Change-Id: I910fe21c42a169e198cdd9340032920f0628a583
2020-09-04e1-xcvr: Add missing gerber output (was uncommitted in my tree)Harald Welte12-0/+20729
2020-09-04big hardware directory re-organization in preparation of ice40 mergeHarald Welte46-0/+0
2020-08-30e1-tracer: repair Excellon drill file (and its desc)Martin Schramm3-232/+232
2020-08-30export e1-tracer eBOM also as csvHarald Welte1-0/+42
2020-08-30export e1-tracer gerber filesHarald Welte12-0/+60277
2020-08-30e1-tracer: Add PDF renderings of schematics and boardHarald Welte2-0/+0
2020-08-30e1-tracer: denote CC-BY-SA 4.0 in schema (adds to SYS#5052)Martin Schramm1-43/+45
2020-08-15e1-tracer: more eBOM atrributes + commit eBOMMartin Schramm3-125/+1088
2020-08-15e1-tracer: collect more BOM atrributesMartin Schramm2-385/+385
2020-08-15e1-tracer: Add various BOM attributesHarald Welte2-190/+190
2020-08-14e1-tracer: further shrink the GND and 3V3 copper inwards left and righte1i-tracer_v1Martin Schramm2-1017/+1337
... and run a local DRC
2020-08-14e1-tracer: update again from ice40 libMartin Schramm1-1/+1
Another pin was found with 'wrong' direction state. Severity of this is low as is shows only warnings in ERC, removing it anyways during verification.
2020-08-14e1-tracer: update from ICE40 lib after minor Eagle pin dir changeMartin Schramm1-2/+2
2020-08-14e1-tracer: start a last renumber (after inserting 4x 0R)Martin Schramm2-340/+340
2020-08-14e1-tracer: annotate jumper JP1 signals in silk screenMartin Schramm1-0/+8
2020-08-14e1-tracer: minor silk screen cosmeticsMartin Schramm1-4/+4
2020-08-14e1-tracer: 4x 0R on R and B LED color selection wiresMartin Schramm2-79/+295
2020-08-14e1-tracer: have more clearance of VBUS trace on PCB edgeMartin Schramm2-907/+914
2020-08-12e1-tracer: add a generic 0603 blue LED type w/ Vf=2.8VMartin Schramm2-6/+7
designating LTST-C193TBKT-5A for now
2020-08-12e1-tracer: improve power bypassing on LIU's VDDT and VDDAMartin Schramm2-465/+567
...by placing 2x 22u per LIU (instead of 68u DNP), shrinking packages from 1206 to 0805
2020-08-12e1-tracer: add 2x 33R series resistors in USB wiresMartin Schramm2-1589/+1715
and * update improved HC73 package * move upper third of PCB (LIUs and XOs) left
2020-08-11e1-tracer: reapir missing VDD_3V3 on serial debug out's TVSMartin Schramm2-37/+10
2020-08-11e1-tracer: 'update' our generic rc lib again to purge '..@1' packagesMartin Schramm2-260/+76
2020-08-11e1-tracer: finish PCBMartin Schramm2-3800/+4356
2020-08-06e1-tracer: state copyright in sch and brdMartin Schramm2-46/+58
2020-08-06e1-tracer: PCB almost readyMartin Schramm2-4091/+6501
... with some room for improvement: LEDs might go to the right of the 2x RJ45
2020-07-27e1-tracer: commit a first schematicMartin Schramm1-0/+14848
2019-12-20increase clearance of ground planes; pad roundnessHarald Welte1-11/+23
2019-12-20enlarge board to have proper mounting holes for mechanical mountingHarald Welte1-653/+656
2019-12-20squash most parts and avoid silk screen overlaps all over the placeHarald Welte1-45/+157
2019-12-20change font to vector / update to v2Harald Welte1-4/+4
2018-05-29e1_xcvr.brd: minor routing improvement on TRING signalMartin Schramm1-21/+26
2018-05-29replace old PULSE_T1094NL footprint, repair pin assignment (solves OSM#3269)Martin Schramm2-225/+243
2018-05-29laforge.lbr: PULSE_T1094NL: better tPlace and tDocu layer (for OSM#3270)Martin Schramm1-8/+15
2018-05-29connect LIU's pin 44 to GND (solves OSM#3247)Martin Schramm2-48/+61
2018-05-18laforge.lbr: repair PULSE_T1094NL footprint and symbol (solves OSM#3270)Martin Schramm1-57/+57
... and OSM#3271. - The transformer symbol is made of two identical coils and hence it is not possible to mark the "2:" side (pins 9-11) separately. But the naming of this coil was changed in a way, that, when invoked, the "2" of the subpart name "TR1-1:2" shows towards the pins 9-11. Maybe we should evolve to a device symbol with two coils merged rather than two identical but separated, then an individual naming could honour the 2:1 side and can not be disturbed by e.g. subsequent mirroring. - Also repaired the name and value designators' layer association.
2012-07-21add E1 tap hardware designHarald Welte14-0/+8925
2012-07-01laforge.lbr: fix amphenol sim reader footprintHarald Welte1-9/+12
2012-07-01major update of laforge.lbr with lots of new componentsHarald Welte1-114/+2715
2012-03-06'new' PCB routing by Christian VogelHarald Welte1-0/+0
2012-02-20major update of laforge.lbr with lots of new componentsHarald Welte1-24/+1379
2012-01-14give parts names without "$", use 47nH as L1 (1206)Harald Welte2-284/+149
2011-12-26approve lots of warnings about thinner wiresHarald Welte1-1/+137
Christan has routed lots of wires thinner than what the network specific rules state. We approve all of them as we don't care about thinner wires.
2011-12-26remove stray GNDIO wire, add junction, approve some warningsHarald Welte1-5/+4
2011-12-26re-route complete board, add PWR jumper, LED series resistorChristian Vogel2-811/+684
2011-12-24add partlist/bomHarald Welte1-0/+56
2011-12-24update schematics and PCB layoutHarald Welte2-0/+0
2011-12-24re-route pcb with LEDsHarald Welte1-280/+391
2011-12-24add two LEDs (power and LOS) plus required transistorHarald Welte1-11/+3039
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