diff options
| author | Kévin Redon <kredon@sysmocom.de> | 2019-01-24 17:15:10 +0100 |
|---|---|---|
| committer | Kévin Redon <kredon@sysmocom.de> | 2019-02-07 15:56:04 +0100 |
| commit | 4a2d8f4773a18d35080c10a63607095dd34901be (patch) | |
| tree | d7cc5d7a6cc2a324586517eb764e267a17d1581a /sysmoOCTSIM/atmel_start_config.atstart | |
| parent | 87af489c19749c16b844ea45ce55e915efcaab28 (diff) | |
switch CPU clock to 120 MHz
use GCLK11 to bring external crystal oscillator XOSC1 from 12 MHz
to 2MHz
use DPLL0 to multiply 2 MHz to 120 MHz.
the division is first needed because the DPLL0 maximum input
frequency is 3.2 MHz
Change-Id: I642e724ec56a376addf21cc58ecd2ef1b40bd116
Diffstat (limited to 'sysmoOCTSIM/atmel_start_config.atstart')
| -rw-r--r-- | sysmoOCTSIM/atmel_start_config.atstart | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 385c890..5e27536 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -646,7 +646,7 @@ drivers: enable_gclk_gen_0: true enable_gclk_gen_1: true enable_gclk_gen_10: false - enable_gclk_gen_11: false + enable_gclk_gen_11: true enable_gclk_gen_2: false enable_gclk_gen_3: true enable_gclk_gen_4: false @@ -665,7 +665,7 @@ drivers: gclk_arch_gen_10_oe: false gclk_arch_gen_10_oov: false gclk_arch_gen_10_runstdby: false - gclk_arch_gen_11_enable: false + gclk_arch_gen_11_enable: true gclk_arch_gen_11_idc: false gclk_arch_gen_11_oe: false gclk_arch_gen_11_oov: false @@ -717,13 +717,13 @@ drivers: gclk_arch_gen_9_runstdby: false gclk_gen_0_div: 1 gclk_gen_0_div_sel: false - gclk_gen_0_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) gclk_gen_10_div: 1 gclk_gen_10_div_sel: false gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) - gclk_gen_11_div: 1 + gclk_gen_11_div: 6 gclk_gen_11_div_sel: false - gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_1_div: 1 gclk_gen_1_div_sel: false gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) @@ -829,24 +829,24 @@ drivers: dfll_mul: 48000 dfll_ref_clock: Generic clock generator 3 enable_dfll: true - enable_fdpll0: false + enable_fdpll0: true enable_fdpll1: false enable_xosc0: false enable_xosc1: true fdpll0_arch_dcoen: false - fdpll0_arch_enable: false + fdpll0_arch_enable: true fdpll0_arch_filter: 0 fdpll0_arch_lbypass: false fdpll0_arch_ltime: No time-out, automatic lock fdpll0_arch_ondemand: false - fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_refclk: XOSC1 clock reference fdpll0_arch_runstdby: false fdpll0_arch_wuf: false fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 0 - fdpll0_ldr: 1463 - fdpll0_ldrfrac: 13 - fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll0_clock_div: 6 + fdpll0_ldr: 59 + fdpll0_ldrfrac: 0 + fdpll0_ref_clock: Generic clock generator 11 fdpll1_arch_dcoen: false fdpll1_arch_enable: false fdpll1_arch_filter: 0 |