diff options
Diffstat (limited to 'misc')
| -rwxr-xr-x | misc/drivers/rtl8187x/rtl8187x.c | 304 | ||||
| -rwxr-xr-x | misc/drivers/rtl8187x/rtl8187x.h | 275 |
2 files changed, 411 insertions, 168 deletions
diff --git a/misc/drivers/rtl8187x/rtl8187x.c b/misc/drivers/rtl8187x/rtl8187x.c index 59e06069a3..7504008c71 100755 --- a/misc/drivers/rtl8187x/rtl8187x.c +++ b/misc/drivers/rtl8187x/rtl8187x.c @@ -811,6 +811,10 @@ static inline int rtl8187x_cfgdesc(FAR struct rtl8187x_state_s *priv, /* Check for a bulk endpoint. */ +#warning "Review needed" +/* For RTL8187B, the Linux driver hardcodes EP 3 for receiving and EP 2 for transmitting. + * Otherwise, it uses EP 1 receiving and some other EP for transmitting (maybe 12). + */ if ((epdesc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_BULK) { /* Yes.. it is a bulk endpoint. IN or OUT? */ @@ -1893,6 +1897,11 @@ static int rtl8187x_transmit(FAR struct rtl8187x_state_s *priv) (0 << 8); /* retry lim */ txdesc->retry = rtl8187x_host2le32(retry); +#ifdef CONFIG_RTL8187B +#warning "This number is bogus" + txdesc->txduration = 40; +#endif + /* And transfer the packet */ ret = DRVR_TRANSFER(priv->hcd, priv->epout, priv->txbuffer, datlen + SIZEOF_TXDESC); @@ -2116,6 +2125,19 @@ static inline int rtl8187x_receive(FAR struct rtl8187x_state_s *priv, /* Perform signal strength calculation */ +#ifdef CONFIG_RTL8187B +/* Linux has this: + * signal = -4 - ((27 * hdr->agc) >> 6); + * antenna = (hdr->signal >> 7) & 1; + * mactime = le64_to_cpu(hdr->mac_time) + * Otherwise + * signal = 14 - hdr->agc / 2; + * antenna = (hdr->rssi >> 7) & 1; + * mactime = le64_to_cpu(hdr->mac_time + */ +#warning "Signal computations must change for RTL8187B" +#endif + signal = rxdesc->agc >> 1; if (priv->rate) { @@ -3328,6 +3350,81 @@ static void rtl8225z2_rfinit(FAR struct rtl8187x_state_s *priv) } /**************************************************************************** + * Function: rtl8187x_anaparam2on and rtl8187x_anaparamon + * + * Description: + * Chip-specific TX power configuration + * + * Parameters: + * priv - Private driver state information + * channel - The selected channel + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static void rtl8187x_anaparam2on(FAR struct rtl8187x_state_s *priv) +{ + uint8_t regval; + + rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); + regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); + rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, regval | RTL8187X_CONFIG3_ANAPARAMWRITE); +#ifdef CONFIG_RTL8187B + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8187B_RTL8225_ANAPARAM2_ON); +#else + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8187X_RTL8225_ANAPARAM2_ON); +#endif + rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); + rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); +} + +static void rtl8187x_anaparamon(FAR struct rtl8187x_state_s *priv) +{ + uint8_t regval; + + rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); + regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); + rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, regval | RTL8187X_CONFIG3_ANAPARAMWRITE); + +#ifdef CONFIG_RTL8187B + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8187B_RTL8225_ANAPARAM_ON); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8187B_RTL8225_ANAPARAM2_ON); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM3, RTL8187B_RTL8225_ANAPARAM3_ON); +#else + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8187X_RTL8225_ANAPARAM_ON); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8187X_RTL8225_ANAPARAM2_ON); +#endif + + rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); + rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); +} + +static void rtl8187x_anaparamoff(FAR struct rtl8187x_state_s *priv) +{ + uint8_t regval; + + rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); + regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); + rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, regval | RTL8187X_CONFIG3_ANAPARAMWRITE); + +#ifdef CONFIG_RTL8187B + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8187B_RTL8225_ANAPARAM_OFF); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8187B_RTL8225_ANAPARAM2_OFF); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM3, RTL8187B_RTL8225_ANAPARAM3_OFF); +#else + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8187X_RTL8225_ANAPARAM_OFF); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8187X_RTL8225_ANAPARAM2_OFF); +#endif + + rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); + rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); +} + +/**************************************************************************** * Function: rtl8225_settxpower and * * Description: @@ -3377,14 +3474,7 @@ static void rtl8225_settxpower(FAR struct rtl8187x_state_s *priv, int channel) /* anaparam2 on */ - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); - regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval | RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8225_ANAPARAM2_ON); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); + rtl8187x_anaparam2on(priv); rtl8187x_wrphyofdm(priv, 2, 0x42); rtl8187x_wrphyofdm(priv, 6, 0x00); @@ -3440,14 +3530,7 @@ static void rtl8225z2_settxpower(FAR struct rtl8187x_state_s *priv, int channel) /* anaparam2 on */ - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); - regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval | RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8225_ANAPARAM2_ON); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); + rtl8187x_anaparam2on(priv); rtl8187x_wrphyofdm(priv, 2, 0x42); rtl8187x_wrphyofdm(priv, 5, 0x00); @@ -3481,17 +3564,122 @@ static int rtl8187x_reset(struct rtl8187x_state_s *priv) uint8_t regval; int i; +#ifdef CONFIG_RTL8187B + int ret; + + /* Turn on ANAPARAM */ + + rtl8187x_anaparamon(priv) + + /* Reset PLL sequence on 8187B. Realtek note: reduces power + * consumption about 30 mA + */ + + rtl8187x_iowrite8(priv, (uint8_t *)0xFF61, 0x10); + regval = rtl818x_ioread8(priv, (uint8_t *)0xFF62); + rtl8187x_iowrite8(priv, (uint8_t *)0xFF62, regval & ~(1 << 5)); + rtl8187x_iowrite8(priv, (uint8_t *)0xFF62, regval | (1 << 5)); + + ret = rtl8187_cmd_reset(dev); + if (ret != 0) + return ret; + + rtl8187x_anaparamon(priv) + + /* BRSR (Basic Rate Set Register) on 8187B looks to be the same as + * RESP_RATE on 8187L in Realtek sources: each bit should be each + * one of the 12 rates, all are enabled */ + rtl8187x_iowrite16(priv, (__le16 *)0xFF34, 0x0FFF); + + regval = rtl818x_ioread8(priv, &priv->map->CW_CONF); + regval |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT; + rtl8187x_iowrite8(priv, &priv->map->CW_CONF, regval); + + /* Auto Rate Fallback Register (ARFR): 1M-54M setting */ + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFFE0, 0x0FFF, 1); + rtl8187x_iowrite8_idx(priv, (uint8_t *)0xFFE2, 0x00, 1); + + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFFD4, 0xFFFF, 1); + + rtl8187x_iowrite8(priv, &priv->map->EEPROM_CMD, + RTL818X_EEPROM_CMD_CONFIG); + regval = rtl818x_ioread8(priv, &priv->map->CONFIG1); + rtl8187x_iowrite8(priv, &priv->map->CONFIG1, (regval & 0x3F) | 0x80); + rtl8187x_iowrite8(priv, &priv->map->EEPROM_CMD, + RTL818X_EEPROM_CMD_NORMAL); + + rtl8187x_iowrite8(priv, &priv->map->WPA_CONF, 0); + for (i = 0; i < ARRAY_SIZE(rtl8187b_reg_table); i++) { + rtl8187x_iowrite8_idx(priv, + (uint8_t *)(uintptr_t) + (rtl8187b_reg_table[i][0] | 0xFF00), + rtl8187b_reg_table[i][1], + rtl8187b_reg_table[i][2]); + } + + rtl8187x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50); + rtl8187x_iowrite16(priv, &priv->map->INT_MIG, 0); + + rtl8187x_iowrite32_idx(priv, (__le32 *)0xFFF0, 0, 1); + rtl8187x_iowrite32_idx(priv, (__le32 *)0xFFF4, 0, 1); + rtl8187x_iowrite8_idx(priv, (uint8_t *)0xFFF8, 0, 1); + + rtl8187x_iowrite32(priv, &priv->map->RF_TIMING, 0x00004001); + + /* RFSW_CTRL register */ + + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x569A, 2); + + rtl8187x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480); + rtl8187x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488); + rtl8187x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); + msleep(100); + + priv->rf->init(dev); + + regval = RTL818X_CMD_TX_ENABLE | RTL818X_CMD_RX_ENABLE; + rtl8187x_iowrite8(priv, &priv->map->CMD, regval); + rtl8187x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); + + rtl8187x_iowrite8(priv, (uint8_t *)0xFE41, 0xF4); + rtl8187x_iowrite8(priv, (uint8_t *)0xFE40, 0x00); + rtl8187x_iowrite8(priv, (uint8_t *)0xFE42, 0x00); + rtl8187x_iowrite8(priv, (uint8_t *)0xFE42, 0x01); + rtl8187x_iowrite8(priv, (uint8_t *)0xFE40, 0x0F); + rtl8187x_iowrite8(priv, (uint8_t *)0xFE42, 0x00); + rtl8187x_iowrite8(priv, (uint8_t *)0xFE42, 0x01); + + regval = rtl818x_ioread8(priv, (uint8_t *)0xFFDB); + rtl8187x_iowrite8(priv, (uint8_t *)0xFFDB, regval | (1 << 2)); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF72, 0x59FA, 3); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF74, 0x59D2, 3); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF76, 0x59D2, 3); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF78, 0x19FA, 3); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF7A, 0x19FA, 3); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFF7C, 0x00D0, 3); + rtl8187x_iowrite8(priv, (uint8_t *)0xFF61, 0); + rtl8187x_iowrite8_idx(priv, (uint8_t *)0xFF80, 0x0F, 1); + rtl8187x_iowrite8_idx(priv, (uint8_t *)0xFF83, 0x03, 1); + rtl8187x_iowrite8(priv, (uint8_t *)0xFFDA, 0x10); + rtl8187x_iowrite8_idx(priv, (uint8_t *)0xFF4D, 0x08, 2); + + rtl8187x_iowrite32(priv, &priv->map->HSSI_PARA, 0x0600321B); + rtl8187x_iowrite16_idx(priv, (__le16 *)0xFFEC, 0x0800, 1); + + priv->slot_time = 0x9; + priv->aifsn[0] = 2; /* AIFSN[AC_VO] */ + priv->aifsn[1] = 2; /* AIFSN[AC_VI] */ + priv->aifsn[2] = 7; /* AIFSN[AC_BK] */ + priv->aifsn[3] = 3; /* AIFSN[AC_BE] */ + rtl8187x_iowrite8(priv, &priv->map->ACM_CONTROL, 0); + + /* ENEDCA flag must always be set, transmit issues? */ + rtl8187x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA); +#else + /* reset */ - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); - regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval | RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8225_ANAPARAM_ON); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8225_ANAPARAM2_ON); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); + rtl8187x_anaparamon(priv); rtl8187x_iowrite16(priv, RTL8187X_ADDR_INTMASK, 0); @@ -3541,15 +3729,7 @@ static int rtl8187x_reset(struct rtl8187x_state_s *priv) return -ETIMEDOUT; } - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); - regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval | RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8225_ANAPARAM_ON); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8225_ANAPARAM2_ON); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); + rtl8187x_anaparamon(priv); /* Setup card */ @@ -3611,6 +3791,7 @@ static int rtl8187x_reset(struct rtl8187x_state_s *priv) rtl8187x_iowrite8(priv, RTL8187X_ADDR_TALLYSEL, 0x80); rtl8187x_iowrite8(priv, 0xffFF, 0x60); rtl8187x_iowrite8(priv, RTL8187X_ADDR_PGSELECT, regval); +#endif return OK; } @@ -3683,6 +3864,29 @@ static int rtl8187x_start(FAR struct rtl8187x_state_s *priv) return ret; } +#ifdef CONFIG_RTL8187B + + regval = RTL818X_RXCONF_MGMT | RTL818X_RXCONF_DATA | RTL818X_RXCONF_BROADCAST | + RTL818X_RXCONF_NICMAC | RTL818X_RX_ONF_BSSID | + (7 << 13 /* RX FIFO threshold NONE */) | + (7 << 10 /* MAX RX DMA */) | + RTL818X_RXCONF_RX_AUTORESETPHY | RTL818X_RXCONF_ONLYERLPKT | RTL818X_RXCONF_MULTICAST; + rtl8187x_iowrite32(priv, RTL8187X_ADDR_RXCONF, regval); + + regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_TXAGCCTL); + regval &= ~RTL8187X_TXAGCCTL_PERPACKETGAINSHIFT; + regval &= ~RTL8187X_TXAGCCTL_PERPACKETANTSELSHIFT; + regval &= ~RTL8187X_TXAGCCTL_FEEDBACKANT; + rtl8187x_iowrite8(priv, RTL8187X_ADDR_TXAGCCTL, regval); + + regval = RTL818X_TXCONF_HWSEQNUM | RTL818X_TXCONF_DISREQQSIZE | + (7 << 8 /* short retry limit */) | + (7 << 0 /* long retry limit */) | + (7 << 21 /* MAX TX DMA */); + rtl8187x_iowrite32(priv, RTL8187X_ADDR_TXCONF, regval); + +#else + rtl8187x_iowrite16(priv, RTL8187X_ADDR_INTMASK, 0xffff); rtl8187x_iowrite32(priv, RTL8187X_ADDR_MAR0, ~0); @@ -3713,7 +3917,7 @@ static int rtl8187x_start(FAR struct rtl8187x_state_s *priv) regval |= RTL8187X_CMD_TXENABLE; regval |= RTL8187X_CMD_RXENABLE; rtl8187x_iowrite8(priv, RTL8187X_ADDR_CMD, regval); - +#endif return OK; } @@ -3749,15 +3953,7 @@ static void rtl8187x_stop(FAR struct rtl8187x_state_s *priv) /* RF stop */ - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); - regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG3); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval | RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM2, RTL8225_ANAPARAM2_OFF); - rtl8187x_iowrite32(priv, RTL8187X_ADDR_ANAPARAM, RTL8225_ANAPARAM_OFF); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_CONFIG3, - regval & ~RTL8187X_CONFIG3_ANAPARAMWRITE); - rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_NORMAL); + rtl8187x_anaparamoff(priv); rtl8187x_iowrite8(priv, RTL8187X_ADDR_EEPROMCMD, RTL8187X_EEPROMCMD_CONFIG); regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_CONFIG4); @@ -3810,6 +4006,10 @@ static int rtl8187x_setup(FAR struct rtl8187x_state_s *priv) udbg("%.4x%.4x%.4x", permaddr[0], permaddr[1], permaddr[2]); +#define RTL8187X_EEPROM_TXPWRCHAN1 0x16 /* 3 channels */ +#define RTL8187X_EEPROM_TXPWRCHAN6 0x1b /* 2 channels */ +#define RTL8187X_EEPROM_TXPWRCHAN4 0x3d /* 2 channels */ + channel = priv->channels; for (i = 0; i < 3; i++) { @@ -3825,6 +4025,20 @@ static int rtl8187x_setup(FAR struct rtl8187x_state_s *priv) (*channel++).val = txpwr >> 8; } +#ifdef CONFIG_RTL8187B + + rtl8187x_eeprom_read(&priv, RTL8187_EEPROM_TXPWR_CHAN_6, &txpwr); + (*channel++).val = txpwr & 0xff; + + rtl8187x_eeprom_read(&priv, 0x0a, &txpwr); + (*channel++).val = txpwr & 0xff; + + rtl8187x_eeprom_read(&priv, 0x1c, &txpwr); + (*channel++).val = txpwr & 0xff; + (*channel++).val= txpwr + +#else + for (i = 0; i < 2; i++) { rtl8187x_eeprom_read(priv, RTL8187X_EEPROM_TXPWRCHAN6 + i, &txpwr); @@ -3832,6 +4046,8 @@ static int rtl8187x_setup(FAR struct rtl8187x_state_s *priv) (*channel++).val = txpwr >> 8; } +#endif + rtl8187x_eeprom_read(priv, RTL8187X_EEPROM_TXPWRBASE, &priv->rxpwrbase); regval = rtl8187x_ioread8(priv, RTL8187X_ADDR_PGSELECT) & ~1; diff --git a/misc/drivers/rtl8187x/rtl8187x.h b/misc/drivers/rtl8187x/rtl8187x.h index bd35e9cc65..f668276476 100755 --- a/misc/drivers/rtl8187x/rtl8187x.h +++ b/misc/drivers/rtl8187x/rtl8187x.h @@ -253,53 +253,59 @@ /* RT8187x Register Addresses ***********************************************/ +#define RTL8187X_ADDR_MAR0 0xff08 +#define RTL8187X_ADDR_MAR1 0xff0c +#define RTL8187X_ADDR_BRSR 0xff2c +#define RTL8187X_ADDR_RESPRATE 0xff34 +#define RTL8187X_ADDR_CMD 0xff37 +#define RTL8187X_ADDR_INTMASK 0xff3c +#define RTL8187X_ADDR_TXCONF 0xff40 #define RTL8187X_ADDR_RXCONF 0xff44 +#define RTL8187X_ADDR_INTTIMEOUT 0xff48 #define RTL8187X_ADDR_EEPROMCMD 0xff50 +#define RTL8187X_ADDR_CONFIG1 0xff52 +#define RTL8187X_ADDR_ANAPARAM 0xff54 +#define RTL8187X_ADDR_CONFIG3 0xff59 +#define RTL8187X_ADDR_CONFIG4 0xff5a +#define RTL8187X_ADDR_TESTR 0xff5b #define RTL8187X_ADDR_PGSELECT 0xff5e +#define RTL8187X_ADDR_ANAPARAM2 0xff60 +#define RTL8187X_ADDR_PHY0 0xff7c +#define RTL8187X_ADDR_PHY1 0xff7d +#define RTL8187X_ADDR_PHY2 0xff7e +#define RTL8187X_ADDR_PHY3 0xff7f #define RTL8187X_ADDR_RFPINSOUTPUT 0xff80 #define RTL8187X_ADDR_RFPINSENABLE 0xff82 #define RTL8187X_ADDR_RFPINSSELECT 0xff84 #define RTL8187X_ADDR_RFPINSINPUT 0xff86 -#define RTL8187X_ADDR_TESTR 0xff5b -#define RTL8187X_ADDR_TXANTENNA 0xff9f -#define RTL8187X_ADDR_PHY3 0xff7f -#define RTL8187X_ADDR_PHY2 0xff7e -#define RTL8187X_ADDR_PHY1 0xff7d -#define RTL8187X_ADDR_PHY0 0xff7c +#define RTL8187X_ADDR_RFPARA 0xff88 +#define RTL8187X_ADDR_RFTIMING 0xff8c +#define RTL8187X_ADDR_GPENABLE 0xff90 +#define RTL8187X_ADDR_GPIO 0xff91 +#define RTL8187X_ADDR_TXAGCCTL 0xff9c #define RTL8187X_ADDR_TXGAINCCK 0xff9d -#define RTL8187X_ADDR_CONFIG3 0xff59 -#define RTL8187X_ADDR_ANAPARAM2 0xff60 #define RTL8187X_ADDR_TXGAINOFDM 0xff9e - -#define RTL8187X_ADDR_ANAPARAM 0xff54 -#define RTL8187X_ADDR_INTMASK 0xff3c -#define RTL8187X_ADDR_CMD 0xff37 -#define RTL8187X_ADDR_GPIO 0xff91 -#define RTL8187X_ADDR_GPENABLE 0xff90 -#define RTL8187X_ADDR_CONFIG1 0xff52 -#define RTL8187X_ADDR_INTTIMEOUT 0xff48 +#define RTL8187X_ADDR_TXANTENNA 0xff9f #define RTL8187X_ADDR_WPACONF 0xffb0 +#define RTL8187X_ADDR_CWCONF 0xffbc +#define RTL8187X_ADDR_CWVAL 0xffbd #define RTL8187X_ADDR_RATEFALLBACK 0xffbe -#define RTL8187X_ADDR_RESPRATE 0xff34 -#define RTL8187X_ADDR_BRSR 0xff2c -#define RTL8187X_ADDR_RFTIMING 0xff8c -#define RTL8187X_ADDR_RFPARA 0xff88 +#define RTL8187X_ADDR_ANAPARAM3 0xffee #define RTL8187X_ADDR_TALLYSEL 0xfffc -#define RTL8187X_ADDR_INTMASK 0xff3c -#define RTL8187X_ADDR_MAR0 0xff08 -#define RTL8187X_ADDR_MAR1 0xff0c -#define RTL8187X_ADDR_CWCONF 0xffbc -#define RTL8187X_ADDR_TXAGCCTL 0xff9c -#define RTL8187X_ADDR_TXCONF 0xff40 -#define RTL8187X_ADDR_CMD 0xff37 -#define RTL8187X_ADDR_CONFIG4 0xff5a /* Other RTL8187x Register Values ******************************************/ -#define RTL8225_ANAPARAM_ON 0xa0000a59 -#define RTL8225_ANAPARAM2_ON 0x860c7312 -#define RTL8225_ANAPARAM_OFF 0xa00beb59 -#define RTL8225_ANAPARAM2_OFF 0x840dec11 +#define RTL8187X_RTL8225_ANAPARAM_ON 0xa0000a59 +#define RTL8187X_RTL8225_ANAPARAM2_ON 0x860c7312 +#define RTL8187X_RTL8225_ANAPARAM_OFF 0xa00beb59 +#define RTL8187X_RTL8225_ANAPARAM2_OFF 0x840dec11 + +#define RTL8187B_RTL8225_ANAPARAM_ON 0x45090658 +#define RTL8187B_RTL8225_ANAPARAM2_ON 0x727f3f52 +#define RTL8187B_RTL8225_ANAPARAM3_ON 0x00 +#define RTL8187B_RTL8225_ANAPARAM_OFF 0x55480658 +#define RTL8187B_RTL8225_ANAPARAM2_OFF 0x72003f50 +#define RTL8187B_RTL8225_ANAPARAM3_OFF 0x00 /* Standard Helper Macros ***************************************************/ @@ -323,101 +329,104 @@ * Type Definitions ****************************************************************************/ - /* RTL-818x mapping struct */ + /* Linux RTL-818x mapping struct. This structure is not used in this driver + * and will, eventually, be removed. It is retained here now for reference. + * See the RTL8187x_ADDR_* definitions above. + */ struct rtl8187x_csr_s { - uint8_t mac[6]; - uint8_t reserved_0[2]; - uint32_t mar[2]; - uint8_t rx_fifo_count; - uint8_t reserved_1; - uint8_t tx_fifo_count; - uint8_t bqreq; - uint8_t reserved_2[4]; - uint32_t tsft[2]; - uint32_t tlpda; - uint32_t tnpda; - uint32_t thpda; - uint16_t brsr; - uint8_t bssid[6]; - uint8_t resp_rate; - uint8_t eifs; - uint8_t reserved_3[1]; - uint8_t cmd; - uint8_t reserved_4[4]; - uint16_t int_mask; - uint16_t int_status; - uint32_t tx_conf; - uint32_t rx_conf; - uint32_t int_timeout; - uint32_t tbda; - uint8_t eeprom_cmd; - uint8_t config0; - uint8_t config1; - uint8_t config2; - uint32_t anaparam; - uint8_t msr; - uint8_t config3; - uint8_t config4; - uint8_t testr; - uint8_t reserved_9[2]; - uint8_t pgselect; - uint8_t security; - uint32_t anaparam2; - uint8_t reserved_10[12]; - uint16_t beacon_interval; - uint16_t atim_wnd; - uint16_t beacon_interval_time; - uint16_t atimtr_interval; - uint8_t phy_delay; - uint8_t carrier_sense_counter; - uint8_t reserved_11[2]; - uint8_t phy[4]; - uint16_t rfpinsoutput; - uint16_t rfpinsenable; - uint16_t rfpinsselect; - uint16_t rfpinsinput; - uint32_t rf_para; - uint32_t rf_timing; - uint8_t gp_enable; - uint8_t gpio0; - uint8_t gpio1; - uint8_t reserved_12; - uint32_t hssi_para; - uint8_t reserved_13[4]; - uint8_t tx_agc_ctl; - uint8_t tx_gain_cck; - uint8_t tx_gain_ofdm; - uint8_t tx_antenna; - uint8_t reserved_14[16]; - uint8_t wpa_conf; - uint8_t reserved_15[3]; - uint8_t sifs; - uint8_t difs; - uint8_t slot; - uint8_t reserved_16[5]; - uint8_t cw_conf; - uint8_t cw_val; - uint8_t rate_fallback; - uint8_t acm_control; - uint8_t reserved_17[24]; - uint8_t config5; - uint8_t tx_dma_polling; - uint8_t reserved_18[2]; - uint16_t cwr; - uint8_t retry_ctr; - uint8_t reserved_19[3]; - uint16_t int_mig; - uint32_t rdsar; - uint16_t tid_ac_map; - uint8_t reserved_20[4]; - uint8_t anaparam3; - uint8_t reserved_21[5]; - uint16_t femr; - uint8_t reserved_22[4]; - uint16_t tally_cnt; - uint8_t tally_sel; + uint8_t mac[6]; /* 0xff00-0xff05 */ + uint8_t reserved_0[2]; /* 0xff06-0xff07 */ + uint32_t mar[2]; /* RTL8187X_ADDR_MARn 0xff08-0xff0f */ + uint8_t rx_fifo_count; /* 0xff10 */ + uint8_t reserved_1; /* 0xff11 */ + uint8_t tx_fifo_count; /* 0xff12 */ + uint8_t bqreq; /* 0xff13 */ + uint8_t reserved_2[4]; /* 0xff14-0xff17 */ + uint32_t tsft[2]; /* 0xff18-0xff1f */ + uint32_t tlpda; /* 0xff20 */ + uint32_t tnpda; /* 0xff24 */ + uint32_t thpda; /* 0xff28 */ + uint16_t brsr; /* RTL8187X_ADDR_BRSR 0xff2c */ + uint8_t bssid[6]; /* 0xff2e-0xff33 */ + uint8_t resp_rate; /* RTL8187X_ADDR_RESPRATE 0xff34 */ + uint8_t eifs; /* 0xff35 */ + uint8_t reserved_3[1]; /* 0xff36 */ + uint8_t cmd; /* RTL8187X_ADDR_CMD 0xff37 */ + uint8_t reserved_4[4]; /* 0xff38-0xff3b */ + uint16_t int_mask; /* RTL8187X_ADDR_INTMASK 0xff3c */ + uint16_t int_status; /* 0xff3e */ + uint32_t tx_conf; /* RTL8187X_ADDR_TXCONF 0xff40 */ + uint32_t rx_conf; /* RTL8187X_ADDR_RXCONF 0xff44 */ + uint32_t int_timeout; /* RTL8187X_ADDR_INTTIMEOUT 0xff48 */ + uint32_t tbda; /* 0xff4c */ + uint8_t eeprom_cmd; /* RTL8187X_ADDR_EEPROMCMD 0xff50 */ + uint8_t config0; /* 0xff51 */ + uint8_t config1; /* RTL8187X_ADDR_CONFIG1 0xff52 */ + uint8_t config2; /* 0xff53 */ + uint32_t anaparam; /* RTL8187X_ADDR_ANAPARAM 0xff54 */ + uint8_t msr; /* 0xff58 */ + uint8_t config3; /* RTL8187X_ADDR_CONFIG3 0xff59 */ + uint8_t config4; /* RTL8187X_ADDR_CONFIG4 0xff5a */ + uint8_t testr; /* RTL8187X_ADDR_TESTR 0xff5b */ + uint8_t reserved_9[2]; /* 0xff5c-0xff5d */ + uint8_t pgselect; /* RTL8187X_ADDR_PGSELECT 0xff5e */ + uint8_t security; /* 0xff5f */ + uint32_t anaparam2; /* RTL8187X_ADDR_ANAPARAM2 0xff60 */ + uint8_t reserved_10[12]; /* 0xff64-0xff6f */ + uint16_t beacon_interval; /* 0xff70 */ + uint16_t atim_wnd; /* 0xff72 */ + uint16_t beacon_interval_time; /* 0xff74 */ + uint16_t atimtr_interval; /* 0xff76 */ + uint8_t phy_delay; /* 0xff78 */ + uint8_t carrier_sense_counter; /* 0xff79 */ + uint8_t reserved_11[2]; /* 0xff7a-0xff7b */ + uint8_t phy[4]; /* RTL8187X_ADDR_PHYn 0xff7c-0xff7f */ + uint16_t rfpinsoutput; /* RTL8187X_ADDR_RFPINSOUTPUT 0xff80 */ + uint16_t rfpinsenable; /* RTL8187X_ADDR_RFPINSENABLE 0xff82 */ + uint16_t rfpinsselect; /* RTL8187X_ADDR_RFPINSSELECT 0xff84 */ + uint16_t rfpinsinput; /* RTL8187X_ADDR_RFPINSINPUT 0xff86 */ + uint32_t rf_para; /* RTL8187X_ADDR_RFPARA 0xff88 */ + uint32_t rf_timing; /* RTL8187X_ADDR_RFTIMING 0xff8c */ + uint8_t gp_enable; /* RTL8187X_ADDR_GPENABLE 0xff90 */ + uint8_t gpio0; /* RTL8187X_ADDR_GPIO 0xff91 */ + uint8_t gpio1; /* 0xff92 */ + uint8_t reserved_12; /* 0xff93 */ + uint32_t hssi_para; /* 0xff94 */ + uint8_t reserved_13[4]; /* 0xff98-0xff9d */ + uint8_t tx_agc_ctl; /* RTL8187X_ADDR_TXAGCCTL 0xff9c */ + uint8_t tx_gain_cck; /* RTL8187X_ADDR_TXGAINCCK 0xff9d */ + uint8_t tx_gain_ofdm; /* RTL8187X_ADDR_TXGAINOFDM 0xff9e */ + uint8_t tx_antenna; /* RTL8187X_ADDR_TXANTENNA 0xff9f */ + uint8_t reserved_14[16]; /* 0xffa0-0xffaf */ + uint8_t wpa_conf; /* RTL8187X_ADDR_WPACONF 0xffb0 */ + uint8_t reserved_15[3]; /* 0xffb1-0xffb3 */ + uint8_t sifs; /* 0xffb4 */ + uint8_t difs; /* 0xffb5 */ + uint8_t slot; /* 0xffb6 */ + uint8_t reserved_16[5]; /* 0xffb7-0xffbb */ + uint8_t cw_conf; /* RTL8187X_ADDR_CWCONF 0xffbc */ + uint8_t cw_val; /* RTL8187X_ADDR_CWVAL 0xffbd */ + uint8_t rate_fallback; /* RTL8187X_ADDR_RATEFALLBACK 0xffbe */ + uint8_t acm_control; /* 0xffbf */ + uint8_t reserved_17[24]; /* 0xffc0-ffd7 */ + uint8_t config5; /* 0xffd8 */ + uint8_t tx_dma_polling; /* 0xffd9 */ + uint8_t reserved_18[2]; /* 0xffda-0xffdb */ + uint16_t cwr; /* 0xffdc */ + uint8_t retry_ctr; /* 0xffde */ + uint8_t reserved_19[3]; /* 0xffdf-0xffe1 */ + uint16_t int_mig; /* 0xffe2 */ + uint32_t rdsar; /* 0xffe4 */ + uint16_t tid_ac_map; /* 0xffe8 */ + uint8_t reserved_20[4]; /* 0xffea-0xffed */ + uint8_t anaparam3; /* RTL8187X_ADDR_ANAPARAM3 0xffee */ + uint8_t reserved_21[5]; /* 0xffef-0xfff3 */ + uint16_t femr; /* 0xfff4 */ + uint8_t reserved_22[4]; /* 0xfff6-0xfff9 */ + uint16_t tally_cnt; /* 0xfffa */ + uint8_t tally_sel; /* RTL8187X_ADDR_TALLYSEL 0xfffc */ } __attribute__ ((packed)); /* RX and TX descriptors */ @@ -434,6 +443,23 @@ struct rtl8187x_rxdesc_s #define SIZEOF_RXDESC 16 +#ifdef CONFIG_RTL8187B +struct rtl8187x_txdesc_s +{ + uint32_t flags; + uint16_t rtsduration; + uint16_t len; + uint32_t unused1; + uint16_t unused2; + uint16_t txduration; + uint32_t unused3; + uint32_t retry; + uint32_t unused4[2]; +} __attribute__((packed)); + +#define SIZEOF_TXDESC 32 + +#else struct rtl8187x_txdesc_s { uint32_t flags; @@ -443,6 +469,7 @@ struct rtl8187x_txdesc_s } __attribute__((packed)); #define SIZEOF_TXDESC 12 +#endif #endif /* __DRIVERS_NET_RTL8187X_H */ |