diff options
| author | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2011-12-20 18:28:50 +0000 |
|---|---|---|
| committer | patacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679> | 2011-12-20 18:28:50 +0000 |
| commit | 8dbb1a79c9d95737e8c667814f736ed72f1a98c3 (patch) | |
| tree | 9980ed8c980faff4c6299ed381ca32314836aa9d /nuttx/configs/vsn | |
| parent | a1a13d684317cef5ad1d1e117ea417b84a34439a (diff) | |
Finishes the PWM driver for the STM32
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4206 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/configs/vsn')
| -rw-r--r-- | nuttx/configs/vsn/include/board.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/nuttx/configs/vsn/include/board.h b/nuttx/configs/vsn/include/board.h index 9f7ec07565..b47df4d6e7 100644 --- a/nuttx/configs/vsn/include/board.h +++ b/nuttx/configs/vsn/include/board.h @@ -97,11 +97,25 @@ #define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK #define STM32_PCLK2_FREQUENCY STM32_BOARD_HCLK +/* APB2 timers 1 and 8 will receive PCLK2. */ + +#define STM32_APB1_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB1_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) + /* APB1 clock (PCLK1) is HCLK (36MHz) */ #define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK #define STM32_PCLK1_FREQUENCY STM32_BOARD_HCLK +/* APB1 timers 2-4 will receive PCLK1. */ + +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) + /* Timer 1..8 Frequencies */ #define STM32_TIM27_FREQUENCY (STM32_BOARD_HCLK) |