Add support for Olimex STM32-P107 board (contributed by Max Holtzberg)

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@5018 7fd9a85b-ad96-42d3-883c-3090e2eb8679

9 files changed, 227 insertions, 61 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
index b9f30b0ed5..82f1fa5e78 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f107vc_pinmap.h
@@ -89,43 +89,49 @@
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif
 
-#if 0 /* Needs further investigation */
+/* Section 29.3 in the stm32 datasheet (Doc ID 13902 Rev 14) */
+
 #define GPIO_ETH_MDC            (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN1)
 #define GPIO_ETH_MDIO           (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ETH_MIICOL         (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ETH_MIICRSWKUP     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ETH_MIIRXCLK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-
+#define GPIO_ETH_MIICOL         (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ETH_MIICRSWKUP     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ETH_MIIRXCLK       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
 #if defined(CONFIG_STM32_ETH_REMAP)
-#  define GPIO_ETH_MIIRXD0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
-#  define GPIO_ETH_MIIRXD1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
-#  define GPIO_ETH_MIIRXD2      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
-#  define GPIO_ETH_MIIRXD3      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
-#  define GPIO_ETH_MIIRXDV      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
+#  define GPIO_ETH_MIIRXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
+#  define GPIO_ETH_MIIRXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
+#  define GPIO_ETH_MIIRXD2      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN11)
+#  define GPIO_ETH_MIIRXD3      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
+#  define GPIO_ETH_MIIRXDV      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
 #else
-#  define GPIO_ETH_MIIRXD0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-#  define GPIO_ETH_MIIRXD1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-#  define GPIO_ETH_MIIRXD2      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
-#  define GPIO_ETH_MIIRXD3      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
-#  define GPIO_ETH_MIIRXDV      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_ETH_MIIRXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_ETH_MIIRXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
+#  define GPIO_ETH_MIIRXD2      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+#  define GPIO_ETH_MIIRXD3      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#  define GPIO_ETH_MIIRXDV      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
 #endif
 
-#define GPIO_ETH_MIIRXER        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_ETH_MIITXCLK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ETH_MIIRXER        (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_ETH_MIITXCLK       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN3)
 #define GPIO_ETH_MIITXD0        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
 #define GPIO_ETH_MIITXD1        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
 #define GPIO_ETH_MIITXD2        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN2)
 #define GPIO_ETH_MIITXD3        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
 #define GPIO_ETH_MIITXEN        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_ETH_PPSOUT         (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_ETH_RMIICRSDV      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ETH_RMIIREFCLK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ETH_RMIIRXD0       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ETH_RMIIRXD1       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
-#define GPIO_ETH_RMIITXD0       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_ETH_RMIITXD1       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_ETH_RMIITXEN       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_ETH_PPS_OUT        (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_ETH_RMII_REF_CLK   (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#if defined(CONFIG_STM32_ETH_REMAP)
+#  define GPIO_ETH_RMII_CRS_DV    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
+#  define GPIO_ETH_RMII_RXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN9)
+#  define GPIO_ETH_RMII_RXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
+#else
+#  define GPIO_ETH_RMII_CRS_DV    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_ETH_RMII_RXD0      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_ETH_RMII_RXD1      (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
 #endif
+#define GPIO_ETH_RMII_TXD0      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ETH_RMII_TXD1      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_ETH_RMII_TX_EN     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
 
 #if defined(CONFIG_STM32_I2C1_REMAP)
 #  define GPIO_I2C1_SCL         (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
@@ -148,9 +154,7 @@
 #define GPIO_I2S3_SD            (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_I2S3_WS            (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
 
-#if 0 /* Needs further investigation */
 #define GPIO_MCO                (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
-#endif
 
 #if 0 /* Needs further investigation */
 #define GPIO_OTG_FSDM           (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
index e3b0241290..feeeda6dd2 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_gpio.h
@@ -271,6 +271,9 @@
 #  define AFIO_MAPR_SWJ              (1 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
 #  define AFIO_MAPR_SWDP             (2 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 010: JTAG-DP Disabled and SW-DP Enabled */
 #  define AFIO_MAPR_DISAB            (4 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 100: JTAG-DP Disabled and SW-DP Disabled */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define AFIO_MAPR_MII_RMII_SEL     (1 << 23) /* MII or RMII selection */
+#endif
 #define AFIO_MAPR_PD01_REMAP         (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
 #define AFIO_MAPR_CAN_REMAP_SHIFT    (13)      /* Bits 14-13: CAN Alternate function remapping */
 #define AFIO_MAPR_CAN_REMAP_MASK     (3 << AFIO_MAPR_CAN_REMAP_SHIFT)
@@ -278,7 +281,7 @@
 #  define AFIO_MAPR_PB89             (2 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */
 #  define AFIO_MAPR_PD01             (3 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */
 #define AFIO_MAPR_TIM4_REMAP         (1 << 12) /* Bit 12: TIM4 remapping */
-#define AFIO_MAPR_TIM3_REMAP_SHIFT  (10)      /* Bits 11-10: TIM3 remapping */
+#define AFIO_MAPR_TIM3_REMAP_SHIFT   (10)      /* Bits 11-10: TIM3 remapping */
 #define AFIO_MAPR_TIM3_REMAP_MASK    (3 << AFIO_MAPR_TIM3_REMAP_SHIFT)
 #  define AFIO_MAPR_TIM3_NOREMAP     (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
 #  define AFIO_MAPR_TIM3_PARTREMAP   (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
index 31544c99f3..60365b9218 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
@@ -52,7 +52,10 @@
 #define STM32_RCC_APB1ENR_OFFSET    0x001c  /* APB1 Peripheral Clock enable register */
 #define STM32_RCC_BDCR_OFFSET       0x0020  /* Backup domain control register */
 #define STM32_RCC_CSR_OFFSET        0x0024  /* Control/status register */
-#ifdef CONFIG_STM32_VALUELINE
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_RCC_AHBRSTR_OFFSET  0x0028  /* AHB Reset register */
+#endif
+#if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  define STM32_RCC_CFGR2_OFFSET    0x002c  /* Clock configuration register 2 */
 #endif
 
@@ -68,7 +71,10 @@
 #define STM32_RCC_APB1ENR           (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
 #define STM32_RCC_BDCR              (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
 #define STM32_RCC_CSR               (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
-#ifdef CONFIG_STM32_VALUELINE
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define STM32_RCC_AHBRSTR         (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
+#endif
+#if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  define STM32_RCC_CFGR2           (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
 #endif
 
@@ -88,6 +94,12 @@
 #define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock Security System enable */
 #define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
 #define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_CR_PLL2ON             (1 << 26) /* Bit 26: PLL2 enable */
+#  define RCC_CR_PLL2RDY            (1 << 27) /* Bit 27: PLL2 clock ready flag */
+#  define RCC_CR_PLL3ON             (1 << 28) /* Bit 28: PLL3 enable */
+#  define RCC_CR_PLL3RDY            (1 << 29) /* Bit 29: PLL3 ready flag */
+#endif
 
 /* Clock configuration register */
 
@@ -153,12 +165,16 @@
 #  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
 #define RCC_CFGR_USBPRE             (1 << 22) /* Bit 22: USB prescaler */
 #define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 26-24: Microcontroller Clock Output */
-#define RCC_CFGR_MCO_MASK           (7 << RCC_CFGR_MCO_SHIFT)
-#  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT) /* 0xx: No clock */
-#  define RCC_CFGR_SYSCLK           (4 << RCC_CFGR_MCO_SHIFT) /* 100: System clock selected */
-#  define RCC_CFGR_INTCLK           (5 << RCC_CFGR_MCO_SHIFT) /* 101: Internal 8 MHz RC oscillator clock selected */
-#  define RCC_CFGR_EXTCLK           (6 << RCC_CFGR_MCO_SHIFT) /* 110: External 1-25 MHz oscillator clock selected */
-#  define RCC_CFGR_PLLCLKd2         (7 << RCC_CFGR_MCO_SHIFT) /* 111: PLL clock divided by 2 selected */
+#define RCC_CFGR_MCO_MASK           (0x0f << RCC_CFGR_MCO_SHIFT)
+#  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT)  /* 0xx: No clock */
+#  define RCC_CFGR_SYSCLK           (4 << RCC_CFGR_MCO_SHIFT)  /* 100: System clock selected */
+#  define RCC_CFGR_INTCLK           (5 << RCC_CFGR_MCO_SHIFT)  /* 101: Internal 8 MHz RC oscillator clock selected */
+#  define RCC_CFGR_EXTCLK           (6 << RCC_CFGR_MCO_SHIFT)  /* 110: External 1-25 MHz oscillator clock selected */
+#  define RCC_CFGR_PLLCLKd2         (7 << RCC_CFGR_MCO_SHIFT)  /* 111: PLL clock divided by 2 selected */
+#  define RCC_CFGR_PLL2CLK          (8 << RCC_CFGR_MCO_SHIFT)  /* 1000: PLL2 clock selected */
+#  define RCC_CFGR_PLL3CLKd2        (9 << RCC_CFGR_MCO_SHIFT)  /* 1001: PLL3 clock devided by 2 selected */
+#  define RCC_CFGR_XT1              (10 << RCC_CFGR_MCO_SHIFT) /* 1010: external 3-25 MHz oscillator clock selected (for Ethernet) */
+#  define RCC_CFGR_PLL3CLK          (11 << RCC_CFGR_MCO_SHIFT) /* 1011: PLL3 clock selected (for Ethernet) */
 
 /* Clock interrupt register */
 
@@ -231,6 +247,18 @@
 #define RCC_AHBENR_CRCEN            (1 << 6)  /* Bit 6: CRC clock enable */
 #define RCC_AHBENR_FSMCEN           (1 << 8)  /* Bit 8: FSMC clock enable */
 #define RCC_AHBENR_SDIOEN           (1 << 10) /* Bit 10: SDIO clock enable */
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_AHBENR_ETHMACEN       (1 << 14) /* Bit 14: Ethernet MAC clock enable */
+#  define RCC_AHBENR_ETHMACTXEN     (1 << 15) /* Bit 15: Ethernet MAC TX clock enable */
+#  define RCC_AHBENR_ETHMACRXEN     (1 << 16) /* Bit 16: Ethernet MAC RX clock enable */
+#endif
+
+/* AHB peripheral clock reset register (RCC_AHBRSTR) */
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+#  define RCC_AHBRSTR_OTGFSRST      (1 << 12) /* USB OTG FS reset */
+#  define RCC_AHBRSTR_ETHMACRST     (1 << 14) /* Ethernet MAC reset */
+#endif
 
 /* APB2 Peripheral Clock enable register */
 
@@ -301,26 +329,86 @@
 #define RCC_CSR_WWDGRSTF            (1 << 30) /* Bit 30: Window watchdog reset flag */
 #define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */
 
-#ifdef CONFIG_STM32_VALUELINE
-
-/* Clock configuration register 2 */
-
-#  define RCC_CFGR2_PREDIV1d1       0  /* HSE input not divided */
-#  define RCC_CFGR2_PREDIV1d2       1  /* HSE input divided by 2 */
-#  define RCC_CFGR2_PREDIV1d3       2  /* HSE input divided by 3 */
-#  define RCC_CFGR2_PREDIV1d4       3  /* HSE input divided by 4 */
-#  define RCC_CFGR2_PREDIV1d5       4  /* HSE input divided by 5 */
-#  define RCC_CFGR2_PREDIV1d6       5  /* HSE input divided by 6 */
-#  define RCC_CFGR2_PREDIV1d7       6  /* HSE input divided by 7 */
-#  define RCC_CFGR2_PREDIV1d8       7  /* HSE input divided by 8 */
-#  define RCC_CFGR2_PREDIV1d9       8  /* HSE input divided by 9 */
-#  define RCC_CFGR2_PREDIV1d10      9  /* HSE input divided by 10 */
-#  define RCC_CFGR2_PREDIV1d11      10 /* HSE input divided by 11 */
-#  define RCC_CFGR2_PREDIV1d12      11 /* HSE input divided by 12 */
-#  define RCC_CFGR2_PREDIV1d13      12 /* HSE input divided by 13 */
-#  define RCC_CFGR2_PREDIV1d14      13 /* HSE input divided by 14 */
-#  define RCC_CFGR2_PREDIV1d15      14 /* HSE input divided by 15 */
-#  define RCC_CFGR2_PREDIV1d16      15 /* HSE input divided by 16 */
+#if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)
+
+/* Clock configuration register 2 (For connectivity line only) */
+
+#define RCC_CFGR2_PREDIV1_SHIFT     (0)
+#define RCC_CFGR2_PREDIV1_MASK      (0x0f << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d1       (0 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d2       (1 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d3       (2 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d4       (3 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d5       (4 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d6       (5 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d7       (6 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d8       (7 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d9       (8 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d10      (9 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d11      (10 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d12      (11 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d13      (12 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d14      (13 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d15      (14 << RCC_CFGR2_PREDIV1_SHIFT)
+#  define RCC_CFGR2_PREDIV1d16      (15 << RCC_CFGR2_PREDIV1_SHIFT)
+
+#define RCC_CFGR2_PREDIV2_SHIFT     (4)
+#define RCC_CFGR2_PREDIV2_MASK      (0x0f << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d1       (0 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d2       (1 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d3       (2 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d4       (3 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d5       (4 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d6       (5 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d7       (6 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d8       (7 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d9       (8 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d10      (9 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d11      (10 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d12      (11 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d13      (12 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d14      (13 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d15      (14 << RCC_CFGR2_PREDIV2_SHIFT)
+#  define RCC_CFGR2_PREDIV2d16      (15 << RCC_CFGR2_PREDIV2_SHIFT)
+
+#define RCC_CFGR2_PLL2MUL_SHIFT     (8)
+#define RCC_CFGR2_PLL2MUL_MASK      (0x0f << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx8       (6 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx9       (7 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx10      (8 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx11      (9 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx12      (10 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx13      (11 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx14      (12 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx16      (14 << RCC_CFGR2_PLL2MUL_SHIFT)
+#  define RCC_CFGR2_PLL2MULx20      (15 << RCC_CFGR2_PLL2MUL_SHIFT)
+
+#define RCC_CFGR2_PLL3MUL_SHIFT     (12)
+#define RCC_CFGR2_PLL3MUL_MASK      (0x0f << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx8       (6 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx9       (7 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx10      (8 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx11      (9 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx12      (10 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx13      (11 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx14      (12 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx16      (14 << RCC_CFGR2_PLL3MUL_SHIFT)
+#  define RCC_CFGR2_PLL3MULx20      (15 << RCC_CFGR2_PLL3MUL_SHIFT)
+
+#define RCC_CFGR2_PREDIV1SRC_SHIFT  (16)
+#define RCC_CFGR2_PREDIV1SRC_MASK   (0x01 << RCC_CFGR2_PREDIV1SRC_SHIFT)
+#  define RCC_CFGR2_PREDIV1SRC_HSE  (0 << RCC_CFGR2_PREDIV1SRC_SHIFT)
+#  define RCC_CFGR2_PREDIV1SRC_PLL2 (1 << RCC_CFGR2_PREDIV1SRC_SHIFT)
+
+#define RCC_CFGR2_I2S2SRC_SHIFT     (17)
+#define RCC_CFGR2_I2S2SRC_MASK      (0x01 << RCC_CFGR2_I2S2SRC_SHIFT)
+#  define RCC_CFGR2_I2S2SRC_SYSCLK  (0 << RCC_CFGR2_I2S2SRC_SHIFT)
+#  define RCC_CFGR2_I2S2SRC_PLL3    (1 << RCC_CFGR2_I2S2SRC_SHIFT)
+
+#define RCC_CFGR2_I2S3SRC_SHIFT     (17)
+#define RCC_CFGR2_I2S3SRC_MASK      (0x01 << RCC_CFGR2_I2S3SRC_SHIFT)
+#  define RCC_CFGR2_I2S3SRC_SYSCLK  (0 << RCC_CFGR2_I2S3SRC_SHIFT)
+#  define RCC_CFGR2_I2S3SRC_PLL3    (1 << RCC_CFGR2_I2S3SRC_SHIFT)
 
 #endif
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
index d18c7e7898..b8d71799fe 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f10xxx_vectors.h
@@ -89,7 +89,8 @@ VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2)         /* Vector 16+12: DMA1 Channel 2
 VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3)         /* Vector 16+13: DMA1 Channel 3 global interrupt */
 VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4)         /* Vector 16+14: DMA1 Channel 4 global interrupt */
 VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5)         /* Vector 16+15: DMA1 Channel 5 global interrupt */
-VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)         /* Vector 16+16: DMA1 Channel 7 global interrupt */
+VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)         /* Vector 16+16: DMA1 Channel 6 global interrupt */
+VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7)         /* Vector 16+17: DMA1 Channel 7 global interrupt */
 VECTOR(stm32_adc12, STM32_IRQ_ADC12)             /* Vector 16+18: ADC1 and ADC2 global interrupt */
 VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX)           /* Vector 16+19: CAN1 TX interrupts */
 VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0)         /* Vector 16+20: CAN1 RX0 interrupts */
@@ -115,6 +116,13 @@ VECTOR(stm32_usart3, STM32_IRQ_USART3)           /* Vector 16+39: USART3 global
 VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510)       /* Vector 16+40: EXTI Line[15:10] interrupts */
 VECTOR(stm32_rtcalr, STM32_IRQ_RTCALRM)          /* Vector 16+41: RTC alarm through EXTI line interrupt */
 VECTOR(stm32_otgfswkup, STM32_IRQ_OTGFSWKUP)     /* Vector 16+42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+UNUSED(STM32_IRQ_RESERVED0)                      /* Vector 16+43: Reserved 0 */
+UNUSED(STM32_IRQ_RESERVED1)                      /* Vector 16+44: Reserved 1 */
+UNUSED(STM32_IRQ_RESERVED2)                      /* Vector 16+55: Reserved 2 */
+UNUSED(STM32_IRQ_RESERVED3)                      /* Vector 16+46: Reserved 3 */
+UNUSED(STM32_IRQ_RESERVED4)                      /* Vector 16+47: Reserved 4 */
+UNUSED(STM32_IRQ_RESERVED5)                      /* Vector 16+48: Reserved 5 */
+UNUSED(STM32_IRQ_RESERVED6)                      /* Vector 16+49: Reserved 6 */
 VECTOR(stm32_tim5, STM32_IRQ_TIM5)               /* Vector 16+50: TIM5 global interrupt */
 VECTOR(stm32_spi3, STM32_IRQ_SPI3 )              /* Vector 16+51: SPI3 global interrupt */
 VECTOR(stm32_uart4 , STM32_IRQ_UART4)            /* Vector 16+52: UART4 global interrupt */
diff --git a/nuttx/arch/arm/src/stm32/stm32_eth.c b/nuttx/arch/arm/src/stm32/stm32_eth.c
index 68ee78fd5f..57d4cc2d33 100644
--- a/nuttx/arch/arm/src/stm32/stm32_eth.c
+++ b/nuttx/arch/arm/src/stm32/stm32_eth.c
@@ -85,7 +85,7 @@
 #  error "Logic to support multiple Ethernet interfaces is incomplete"
 #endif
 
-#ifndef CONFIG_STM32_SYSCFG
+#if !defined(CONFIG_STM32_SYSCFG) && !defined(CONFIG_STM32_CONNECTIVITYLINE)
 #  error "CONFIG_STM32_SYSCFG must be defined in the NuttX configuration"
 #endif
 
@@ -2657,6 +2657,13 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
 
 #elif defined(CONFIG_STM32_RMII)
 
+  /* Setup MCO pin for alternative usage */
+
+#if defined(CONFIG_STM32_RMII_MCO)
+  stm32_configgpio(GPIO_MCO);
+  stm32_mcoconfig(BOARD_CFGR_MCO_SOURCE);
+#endif
+
   /* Select the RMII interface */
 
   stm32_selectrmii();
@@ -2673,7 +2680,7 @@ static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv)
   stm32_configgpio(GPIO_ETH_RMII_RXD1);
   stm32_configgpio(GPIO_ETH_RMII_TXD0);
   stm32_configgpio(GPIO_ETH_RMII_TXD1);
-  stm32_configgpio(GPIO_ETH_RMII_TX_CLK);
+  /* stm32_configgpio(GPIO_ETH_RMII_TX_CLK); not needed? */
   stm32_configgpio(GPIO_ETH_RMII_TX_EN);
 
 #endif
@@ -2704,14 +2711,25 @@ static void stm32_ethreset(FAR struct stm32_ethmac_s *priv)
 {
   uint32_t regval;
 
-  /* Reset the Ethernet on the AHB1 bus */
+  /* Reset the Ethernet on the AHB bus (F1 Connectivity Line) or AHB1 bus (F2
+   * and F4)
+   */
 
+#if defined(CONFIG_STM32_CONNECTIVITYLINE)
+  regval  = stm32_getreg(STM32_RCC_AHBRSTR);
+  regval |= RCC_AHBRSTR_ETHMACRST;
+  stm32_putreg(regval, STM32_RCC_AHBRSTR);
+
+  regval &= ~RCC_AHBRSTR_ETHMACRST;
+  stm32_putreg(regval, STM32_RCC_AHBRSTR);
+#else
   regval  = stm32_getreg(STM32_RCC_AHB1RSTR);
   regval |= RCC_AHB1RSTR_ETHMACRST;
   stm32_putreg(regval, STM32_RCC_AHB1RSTR);
 
   regval &= ~RCC_AHB1RSTR_ETHMACRST;
   stm32_putreg(regval, STM32_RCC_AHB1RSTR);
+#endif
 
   /* Perform a software reset by setting the SR bit in the DMABMR register.
    * This Resets all MAC subsystem internal registers and logic.  After this
diff --git a/nuttx/arch/arm/src/stm32/stm32_rcc.h b/nuttx/arch/arm/src/stm32/stm32_rcc.h
index c4d43db3a7..292eade73b 100644
--- a/nuttx/arch/arm/src/stm32/stm32_rcc.h
+++ b/nuttx/arch/arm/src/stm32/stm32_rcc.h
@@ -117,6 +117,39 @@ static inline void stm32_mco1config(uint32_t source, uint32_t div)
 #endif
 
 /************************************************************************************
+ * Name: stm32_mcoconfig
+ *
+ * Description:
+ *   Selects the clock source to output on MC pin (PA8) for stm32f10xxx.
+ *   PA8 should be configured in alternate function mode.
+ *
+ * Input Parameters:
+ *   source - One of the definitions for the RCC_CFGR_MCO definitions from
+ *     chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, RCC_CFGR_EXTCLK,
+ *     RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1,
+ *     RCC_CFGR_PLL3CLK}
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_STM32_CONNECTIVITYLINE)
+static inline void stm32_mcoconfig(uint32_t source)
+{
+  uint32_t regval;
+
+  /* Set MCO source */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_MCO_MASK);
+  regval |= (source & RCC_CFGR_MCO_MASK);
+  putreg32(regval, STM32_RCC_CFGR);
+}
+#endif
+
+
+/************************************************************************************
  * Name: stm32_mco2config
  *
  * Description:
diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.c b/nuttx/arch/arm/src/stm32/stm32_sdio.c
index b109160a17..57d5f80d96 100644
--- a/nuttx/arch/arm/src/stm32/stm32_sdio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_sdio.c
@@ -1615,7 +1615,7 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
       /* SD normal operation clocking (narrow 1-bit mode) */
 
       case CLOCK_SD_TRANSFER_1BIT:
-        clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN)
+        clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN);
         break;
     }
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_vectors.S b/nuttx/arch/arm/src/stm32/stm32_vectors.S
index b75237e40f..ab4dadb779 100644
--- a/nuttx/arch/arm/src/stm32/stm32_vectors.S
+++ b/nuttx/arch/arm/src/stm32/stm32_vectors.S
@@ -143,6 +143,9 @@ stm32_vectors:
 #undef VECTOR
 #define VECTOR(l,i) .word l
 
+#undef UNUSED
+#define UNUSED(i) .word stm32_reserved
+
 #if defined(CONFIG_STM32_STM32F10XX)
 #  include "chip/chip/stm32f10xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
@@ -176,6 +179,9 @@ handlers:
 #undef VECTOR
 #define VECTOR(l,i) HANDLER l, i
 
+#undef UNUSED
+#define UNUSED(i)
+
 #if defined(CONFIG_STM32_STM32F10XX)
 #  include "chip/chip/stm32f10xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
diff --git a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
index 516b026fb0..10b8572cf0 100644
--- a/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/nuttx/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -144,6 +144,12 @@ static inline void rcc_enableahb(void)
   regval |=  RCC_AHBENR_SDIOEN;
 #endif
 
+#if defined(CONFIG_STM32_ETHMAC) && defined(CONFIG_STM32_CONNECTIVITYLINE)
+  /* Ethernet clock enable */
+
+  regval |= (RCC_AHBENR_ETHMACEN | RCC_AHBENR_ETHMACTXEN | RCC_AHBENR_ETHMACRXEN);
+#endif
+
   putreg32(regval, STM32_RCC_AHBENR);   /* Enable peripherals */
 }