SDIO fixes for the STM32 F2 from Gary Teravskis and Scott Rondestvedt

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4973 7fd9a85b-ad96-42d3-883c-3090e2eb8679

4 files changed, 59 insertions, 53 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
index 1c10d5a744..2c8587855e 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
@@ -404,15 +404,15 @@
 /* SDIO */
 
 #define GPIO_SDIO_CK          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
-#define GPIO_SDIO_CMD         (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2)
-#define GPIO_SDIO_D0          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8)
-#define GPIO_SDIO_D1          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9)
-#define GPIO_SDIO_D2          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10)
-#define GPIO_SDIO_D3          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11)
-#define GPIO_SDIO_D4          (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_SDIO_D5          (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9)
-#define GPIO_SDIO_D6          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_SDIO_D7          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_SDIO_CMD         (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
+#define GPIO_SDIO_D0          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_SDIO_D1          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_SDIO_D2          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_SDIO_D3          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_SDIO_D4          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_SDIO_D5          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_SDIO_D6          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_SDIO_D7          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
 
 /* SPI */
 
diff --git a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
index 50e38f6ba1..a588b56a27 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
@@ -1,8 +1,8 @@
 /************************************************************************************
  * arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
  *
- *   Copyright (C) 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -62,7 +62,7 @@
  * The driver will then automatically configre PA11 as the CAN1 RX pin.
  */
 
-/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! 
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
  * Additional effort is required to select specific GPIO options such as frequency,
  * open-drain/push-pull, and pull-up/down!  Just the basics are defined for most
  * pins in this file.
@@ -404,15 +404,15 @@
 /* SDIO */
 
 #define GPIO_SDIO_CK          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
-#define GPIO_SDIO_CMD         (GPIO_ALT|GPIO_AF12|GPIO_PORTD|GPIO_PIN2)
-#define GPIO_SDIO_D0          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN8)
-#define GPIO_SDIO_D1          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN9)
-#define GPIO_SDIO_D2          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN10)
-#define GPIO_SDIO_D3          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN11)
-#define GPIO_SDIO_D4          (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_SDIO_D5          (GPIO_ALT|GPIO_AF12|GPIO_PORTB|GPIO_PIN9)
-#define GPIO_SDIO_D6          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_SDIO_D7          (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_SDIO_CMD         (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
+#define GPIO_SDIO_D0          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_SDIO_D1          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_SDIO_D2          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_SDIO_D3          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_SDIO_D4          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_SDIO_D5          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_SDIO_D6          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_SDIO_D7          (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
 
 /* SPI */
 
diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.c b/nuttx/arch/arm/src/stm32/stm32_sdio.c
index 1242398350..b109160a17 100644
--- a/nuttx/arch/arm/src/stm32/stm32_sdio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_sdio.c
@@ -570,15 +570,20 @@ static inline void stm32_setclkcr(uint32_t clkcr)
   /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
 
   regval &= ~(SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
-              SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN);
+              SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN|
+              SDIO_CLKCR_CLKEN);
 
   /* Replace with user provided settings */
 
   clkcr  &=  (SDIO_CLKCR_CLKDIV_MASK|SDIO_CLKCR_PWRSAV|SDIO_CLKCR_BYPASS|
-              SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN);
+              SDIO_CLKCR_WIDBUS_MASK|SDIO_CLKCR_NEGEDGE|SDIO_CLKCR_HWFC_EN|
+              SDIO_CLKCR_CLKEN);
+
   regval |=  clkcr;
   putreg32(regval, STM32_SDIO_CLKCR);
-  fvdbg("CLKCR: %08x\n", getreg32(STM32_SDIO_CLKCR));
+
+  fvdbg("CLKCR: %08x PWR: %08x\n",
+        getreg32(STM32_SDIO_CLKCR), getreg32(STM32_SDIO_POWER));
 }
 
 /****************************************************************************
@@ -1508,12 +1513,8 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
 
   /* Configure the SDIO peripheral */
 
-  stm32_setclkcr(STM32_CLCKCR_INIT);
+  stm32_setclkcr(STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN);
   stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON);
-
-  /* (Re-)enable clocking */
-
-  putreg32(1, SDIO_CLKCR_CLKEN_BB);
   irqrestore(flags);
 
   fvdbg("CLCKR: %08x POWER: %08x\n",
@@ -1581,41 +1582,46 @@ static void stm32_widebus(FAR struct sdio_dev_s *dev, bool wide)
 static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
 {
   uint32_t clckr;
-  uint32_t enable = 1;
 
   switch (rate)
     {
-    default:
-    case CLOCK_SDIO_DISABLED:     /* Clock is disabled */
-      clckr  = STM32_CLCKCR_INIT;
-      enable = 0;
-      return;
+      /* Disable clocking (with default ID mode divisor) */
 
-    case CLOCK_IDMODE:            /* Initial ID mode clocking (<400KHz) */
-      clckr  = STM32_CLCKCR_INIT;
-      break;
+      default:
+      case CLOCK_SDIO_DISABLED:
+        clckr = STM32_CLCKCR_INIT;
+        return;
 
-    case CLOCK_MMC_TRANSFER:      /* MMC normal operation clocking */
-      clckr  = SDIO_CLKCR_MMCXFR;
-      break;
+      /* Enable in initial ID mode clocking (<400KHz) */
+
+      case CLOCK_IDMODE:            
+        clckr = (STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN);
+        break;
 
-    case CLOCK_SD_TRANSFER_4BIT:  /* SD normal operation clocking (wide 4-bit mode) */
+      /* Enable in MMC normal operation clocking */
+
+      case CLOCK_MMC_TRANSFER:
+        clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN);
+        break;
+
+      /* SD normal operation clocking (wide 4-bit mode) */
+
+      case CLOCK_SD_TRANSFER_4BIT:
 #ifndef CONFIG_SDIO_WIDTH_D1_ONLY
-      clckr  = SDIO_CLCKR_SDWIDEXFR;
-      break;
+        clckr = (SDIO_CLCKR_SDWIDEXFR | SDIO_CLKCR_CLKEN);
+        break;
 #endif
 
-    case CLOCK_SD_TRANSFER_1BIT:  /* SD normal operation clocking (narrow 1-bit mode) */
-      clckr  = SDIO_CLCKR_SDXFR;
-      break;
-    };
+      /* SD normal operation clocking (narrow 1-bit mode) */
 
-  /* Set the new clock frequency and make sure that the clock is enabled or
-   * disabled, whatever the case.
-   */
+      case CLOCK_SD_TRANSFER_1BIT:
+        clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN)
+        break;
+    }
+
+  /* Set the new clock frequency along with the clock enable/disable bit */
 
   stm32_setclkcr(clckr);
-  putreg32(enable, SDIO_CLKCR_CLKEN_BB);
 }
 
 /****************************************************************************
diff --git a/nuttx/arch/arm/src/stm32/stm32_sdio.h b/nuttx/arch/arm/src/stm32/stm32_sdio.h
index 46fbe8a951..ceeb56f0dd 100644
--- a/nuttx/arch/arm/src/stm32/stm32_sdio.h
+++ b/nuttx/arch/arm/src/stm32/stm32_sdio.h
@@ -2,7 +2,7 @@
  * arch/arm/src/stm32/stm32_sdio.h
  *
  *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions