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authorpatacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679>2009-05-12 22:15:49 +0000
committerpatacongo <patacongo@7fd9a85b-ad96-42d3-883c-3090e2eb8679>2009-05-12 22:15:49 +0000
commit0b74d638046b6b736f7cf86675c38d84908f87c7 (patch)
tree40f400e9c2a21a75c596cb2c0e1d05e8e058eff8 /nuttx/arch/arm/src/lm3s/chip.h
parent8320444101b3c5add0466ccc2f38d459fbf5a27f (diff)
Flesh out LM3S9618 interrupt control logic
git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@1774 7fd9a85b-ad96-42d3-883c-3090e2eb8679
Diffstat (limited to 'nuttx/arch/arm/src/lm3s/chip.h')
-rw-r--r--nuttx/arch/arm/src/lm3s/chip.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/nuttx/arch/arm/src/lm3s/chip.h b/nuttx/arch/arm/src/lm3s/chip.h
index a5175a49fc..f6ff0c16a1 100644
--- a/nuttx/arch/arm/src/lm3s/chip.h
+++ b/nuttx/arch/arm/src/lm3s/chip.h
@@ -53,6 +53,16 @@
* Definitions
************************************************************************************/
+/* The LM3S6918 only supports 8 priority levels. The hardware priority mechanism
+ * will only look at the upper N bits of the 8-bit priority level (where N is 3 for
+ * the Stellaris family), so any prioritization must be performed in those bits.
+ * The default priority level is set to the middle value
+ */
+
+#define NVIC_SYSH_PRIORITY_MIN 0x00
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80
+#define NVIC_SYSH_PRIORITY_MAX 0xe0
+
/************************************************************************************
* Public Types
************************************************************************************/