Finish STM32 IWDG and WWDG watchdog timer drivers

git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4613 7fd9a85b-ad96-42d3-883c-3090e2eb8679

5 files changed, 386 insertions, 32 deletions

diff --git a/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h b/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h
index 64ef2e0ac6..a3ca75205e 100644
--- a/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h
+++ b/nuttx/arch/arm/src/stm32/chip/stm32_wdg.h
@@ -116,6 +116,8 @@
 
 #define WWDG_CFR_W_SHIFT        (0)       /* Bits 6:0 W[6:0] 7-bit window value */
 #define WWDG_CFR_W_MASK         (0x7f << WWDG_CFR_W_SHIFT)
+#  define WWDG_CFR_W_MAX        (0x3f << WWDG_CFR_W_SHIFT)
+#  define WWDG_CFR_W_RESET      (0x40 << WWDG_CFR_W_SHIFT)
 #define WWDG_CFR_WDGTB_SHIFT    (7)       /* Bits 8:7 [1:0]: Timer Base */
 #define WWDG_CFR_WDGTB_MASK     (3 << WWDG_CFR_WDGTB_SHIFT)
 #  define WWDG_CFR_PCLK1        (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
diff --git a/nuttx/arch/arm/src/stm32/stm32_gpio.c b/nuttx/arch/arm/src/stm32/stm32_gpio.c
index f3411f1e47..143e48a2c8 100644
--- a/nuttx/arch/arm/src/stm32/stm32_gpio.c
+++ b/nuttx/arch/arm/src/stm32/stm32_gpio.c
@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/arm/src/stm32/stm32_gpio.c
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2011 Uros Platise. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *           Uros Platise <uros.platise@isotel.eu>
@@ -127,7 +127,7 @@ static inline void stm32_gpioremap(void)
 #ifdef CONFIG_STM32_JTAG_FULL_ENABLE
   /* The reset default */
 #elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
-  val |= AFIO_MAPR_SWJ;    /* enabled but without JNTRST */
+  val |= AFIO_MAPR_SWJ;       /* enabled but without JNTRST */
 #elif CONFIG_STM32_JTAG_SW_ENABLE
   val |= AFIO_MAPR_SWDP;      /* set JTAG-DP disabled and SW-DP enabled */
 #else
diff --git a/nuttx/arch/arm/src/stm32/stm32_iwdg.c b/nuttx/arch/arm/src/stm32/stm32_iwdg.c
index 081386e98c..ca97963899 100644
--- a/nuttx/arch/arm/src/stm32/stm32_iwdg.c
+++ b/nuttx/arch/arm/src/stm32/stm32_iwdg.c
@@ -47,6 +47,7 @@
 
 #include "up_arch.h"
 #include "stm32_rcc.h"
+#include "chip/stm32_dbgmcu.h"
 #include "stm32_wdg.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG)
@@ -315,12 +316,16 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
 
   DEBUGASSERT(priv);
 
+  /* Return the status bit */
+
   status->flags = WDFLAGS_RESET;
   if (priv->started)
     {
       status->flags |= WDFLAGS_ACTIVE;
     }
 
+  /* Return the actual timeout is milliseconds */
+
   status->timeout = priv->timeout;
 
   /* I am not sure what will be returned when reading from the reload register.
@@ -374,11 +379,12 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
        * PR = 4 -> Divider = 64  = 1 << 6
        * PR = 5 -> Divider = 128 = 1 << 7
        * PR = 6 -> Divider = 256 = 1 << 8
+       * PR = n -> Divider       = 1 << (n+2)
        */
 
       shift = pr + 2;
 
-      /* Is the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
+      /* Get the IWDG counter frequency in Hz. For a nominal 32Khz LSI clock,
        * this is value in the range of 7500 and 125.
        */
 
@@ -471,6 +477,10 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
 {
   FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
 
+  /* NOTE we assume that clocking to the IWDG has already been provided by
+   * the RCC initialization logic.
+   */
+
   /* Initialize the driver state structure. */
 
   priv->ops = &g_wdgops;
@@ -496,6 +506,21 @@ void stm32_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
   /* Register the watchdog driver as /dev/watchdog0 */
 
   (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+
+  /* When the microcontroller enters debug mode (Cortex™-M4F core halted),
+   * the IWDG counter either continues to work normally or stops, depending
+   * on DBG_WIDG_STOP configuration bit in DBG module.
+   */
+
+#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
+    defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
+    defined(CONFIG_STM32_JTAG_SW_ENABLE)
+    {
+      uint32_t cr = getreg32(STM32_DBGMCU_CR);
+      cr |= DBGMCU_CR_IWDGSTOP;
+      putreg32(cr, STM32_DBGMCU_CR);
+    }
+#endif
 }
 
 #endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */
diff --git a/nuttx/arch/arm/src/stm32/stm32_wwdg.c b/nuttx/arch/arm/src/stm32/stm32_wwdg.c
index b116aea289..7db40b228c 100644
--- a/nuttx/arch/arm/src/stm32/stm32_wwdg.c
+++ b/nuttx/arch/arm/src/stm32/stm32_wwdg.c
@@ -44,8 +44,10 @@
 #include <errno.h>
 
 #include <nuttx/watchdog.h>
+#include <arch/board/board.h>
 
 #include "up_arch.h"
+#include "chip/stm32_dbgmcu.h"
 #include "stm32_wdg.h"
 
 #if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG)
@@ -53,6 +55,12 @@
 /****************************************************************************
  * Pre-Processor Definitions
  ****************************************************************************/
+/* Configuration ************************************************************/
+
+#ifndef CONFIG_STM32_WWDG_DEFTIMOUT
+#  define CONFIG_STM32_WWDG_DEFTIMOUT 3000 /* Three seconds */
+#endif
+
 
 /****************************************************************************
  * Private Types
@@ -65,6 +73,12 @@
 struct stm32_lowerhalf_s
 {
   FAR const struct watchdog_ops_s  *ops;  /* Lower half operations */
+  xcpt_t   handler;  /* Current EWI interrupt handler */
+  uint32_t timeout;  /* The actual timeout value */
+  uint32_t fwwdg;    /* WWDG clock frequency */
+  bool     started;  /* The timer has been started */
+  uint8_t  reload;   /* The 7-bit reload field reset value */
+  uint8_t  window;   /* The 7-bit window (W) field value */
 };
 
 /****************************************************************************
@@ -73,12 +87,18 @@ struct stm32_lowerhalf_s
 /* Register operations ******************************************************/
 
 #if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG)
-static uint32_t stm32_getreg(uint32_t addr);
-static void     stm32_putreg(uint32_t val, uint32_t addr);
+static uint16_t stm32_getreg(uint32_t addr);
+static void     stm32_putreg(uint16_t val, uint32_t addr);
 #else
 # define        stm32_getreg(addr)     getreg32(addr)
 # define        stm32_putreg(val,addr) putreg32(val,addr)
 #endif
+static void     stm32_setwindow(FAR struct stm32_lowerhalf_s *priv,
+                  uint8_t window);
+
+/* Interrupt hanlding *******************************************************/
+
+static int      stm32_interrupt(int irq, FAR void *context);
 
 /* "Lower half" driver methods **********************************************/
 
@@ -127,15 +147,15 @@ static struct stm32_lowerhalf_s g_wdgdev;
  ****************************************************************************/
 
 #if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG)
-static uint32_t stm32_getreg(uint32_t addr)
+static uint16_t stm32_getreg(uint16_t addr)
 {
-  static uint32_t prevaddr = 0;
-  static uint32_t preval = 0;
-  static uint32_t count = 0;
+  static uint16_t prevaddr = 0;
+  static uint16_t count = 0;
+  static uint16_t preval = 0;
 
   /* Read the value from the register */
 
-  uint32_t val = getreg32(addr);
+  uint16_t val = getreg16(addr);
 
   /* Is this the same value that we read from the same registe last time?  Are
    * we polling the register?  If so, suppress some of the output.
@@ -175,7 +195,7 @@ static uint32_t stm32_getreg(uint32_t addr)
 
   /* Show the register value read */
 
-  lldbg("%08x->%08x\n", addr, val);
+  lldbg("%08x->%04x\n", addr, val);
   return val;
 }
 #endif
@@ -189,19 +209,93 @@ static uint32_t stm32_getreg(uint32_t addr)
  ****************************************************************************/
 
 #if defined(CONFIG_STM32_WWDG_REGDEBUG) && defined(CONFIG_DEBUG)
-static void stm32_putreg(uint32_t val, uint32_t addr)
+static void stm32_putreg(uint16_t val, uint32_t addr)
 {
   /* Show the register value being written */
 
-  lldbg("%08x<-%08x\n", addr, val);
+  lldbg("%08x<-%04x\n", addr, val);
 
   /* Write the value */
 
-  putreg32(val, addr);
+  putreg16(val, addr);
 }
 #endif
 
 /****************************************************************************
+ * Name: stm32_setwindow
+ *
+ * Description:
+ *   Set the CFR window value. The window value is compared to the down-
+ *   counter when the counter is updated.  The WWDG counter should be updated
+ *   only when the counter is below this window value (and greater than 64)
+ *   otherwise a reset will be generated
+ *
+ ****************************************************************************/
+
+static void stm32_setwindow(FAR struct stm32_lowerhalf_s *priv, uint8_t window)
+{
+  uint16_t regval;
+
+  /* Set W[6:0] bits according to selected window value */
+
+  regval = stm32_getreg(STM32_WWDG_CFR);
+  regval &= ~WWDG_CFR_W_MASK;
+  regval |= window << WWDG_CFR_W_SHIFT;
+  stm32_putreg(regval, STM32_WWDG_CFR);
+
+  /* Remember the window setting */
+
+  priv->window = window;
+}
+
+/****************************************************************************
+ * Name: stm32_interrupt
+ *
+ * Description:
+ *   WWDG early warning interrupt
+ *
+ * Input Parameters:
+ *   Usual interrupt handler arguments.
+ *
+ * Returned Values:
+ *   Always returns OK.
+ *
+ ****************************************************************************/
+
+static int stm32_interrupt(int irq, FAR void *context)
+{
+  FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
+  uint16_t regval;
+
+  /* Check if the EWI interrupt is really pending */
+
+  regval = stm32_getreg(STM32_WWDG_SR);
+  if ((regval & WWDG_SR_EWIF) != 0)
+    {
+      /* Is there a registered handler? */
+
+      if (priv->handler)
+        {
+          /* Yes... NOTE:  This interrupt service routine (ISR) must reload
+           * the WWDG counter to prevent the reset.  Otherwise, we will reset
+           * upon return.
+           */
+
+          priv->handler(irq, context);
+        }
+
+      /* The EWI interrupt is cleared by writing '0' to the EWIF bit in the
+       * WWDG_SR register.
+       */
+
+      regval &= ~WWDG_SR_EWIF;
+      stm32_putreg(regval, STM32_WWDG_SR);
+    }
+
+  return OK;
+}
+
+/****************************************************************************
  * Name: stm32_start
  *
  * Description:
@@ -220,9 +314,16 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
 {
   FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
 
+  /* The watchdog is always disabled after a reset. It is enabled by setting
+   * the WDGA bit in the WWDG_CR register, then it cannot be disabled again
+   * except by a reset.
+   */
+
   DEBUGASSERT(priv);
-#warning "Missing logic"
-  return -ENOSYS;
+
+  stm32_putreg(WWDG_CR_WDGA | WWDG_CFR_W_RESET | priv->reload, STM32_WWDG_CR);
+  priv->started = true;
+  return OK;
 }
 
 /****************************************************************************
@@ -242,10 +343,11 @@ static int stm32_start(FAR struct watchdog_lowerhalf_s *lower)
 
 static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
 {
-  FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
+  /* The watchdog is always disabled after a reset. It is enabled by setting
+   * the WDGA bit in the WWDG_CR register, then it cannot be disabled again
+   * except by a reset.
+   */
 
-  DEBUGASSERT(priv);
-#warning "Missing logic"
   return -ENOSYS;
 }
 
@@ -257,6 +359,12 @@ static int stm32_stop(FAR struct watchdog_lowerhalf_s *lower)
  *   imminent watchdog timeouts.  This is sometimes referred as "pinging"
  *   the atchdog timer or "petting the dog".
  *
+ *   The application program must write in the WWDG_CR register at regular
+ *   intervals during normal operation to prevent an MCU reset. This operation
+ *   must occur only when the counter value is lower than the window register
+ *   value. The value to be stored in the WWDG_CR register must be between
+ *   0xff and 0xC0:
+ *
  * Input Parameters:
  *   lower - A pointer the publicly visible representation of the "lower
  *           driver state structure.
@@ -271,8 +379,13 @@ static int stm32_keepalive(FAR struct watchdog_lowerhalf_s *lower)
   FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
 
   DEBUGASSERT(priv);
-#warning "Missing logic"
-  return -ENOSYS;
+
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+   * a read-modify-write; writing a 0 to WDGA bit does nothing.
+   */
+
+  stm32_putreg((WWDG_CFR_W_RESET | priv->reload), STM32_WWDG_CR);
+  return OK;
 }
 
 /****************************************************************************
@@ -295,10 +408,35 @@ static int stm32_getstatus(FAR struct watchdog_lowerhalf_s *lower,
                            FAR struct watchdog_status_s *status)
 {
   FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
+  uint32_t elapsed;
+  uint16_t reload;
 
   DEBUGASSERT(priv);
-#warning "Missing logic"
-  return -ENOSYS;
+
+  /* Return the status bit */
+
+  status->flags = WDFLAGS_RESET;
+  if (priv->started)
+    {
+      status->flags |= WDFLAGS_ACTIVE;
+    }
+ 
+  if (priv->handler)
+    {
+      status->flags |= WDFLAGS_CAPTURE;
+    }
+
+  /* Return the actual timeout is milliseconds */
+
+  status->timeout = priv->timeout;
+
+  /* Get the time remaining until the watchdog expires (in milliseconds) */
+
+  reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f;
+  elapsed = priv->reload - reload;
+  status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1);
+
+  return OK;
 }
 
 /****************************************************************************
@@ -323,8 +461,97 @@ static int stm32_settimeout(FAR struct watchdog_lowerhalf_s *lower,
   FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
 
   DEBUGASSERT(priv);
-#warning "Missing logic"
-  return -ENOSYS;
+  uint32_t fwwdg;
+  uint32_t reload;
+  uint16_t regval;
+  int wdgtb;
+
+   /* Determine prescaler value.
+   *
+   * Fwwdg = PCLK1/4096/prescaler.
+   *
+   * Where
+   *  Fwwwdg is the frequency of the WWDG clock
+   *  prescaler is one of {1, 2, 4, or 8}
+   */
+
+  /* Select the smallest prescaler that will result in a reload field value that is
+   * less than the maximum.
+   */
+
+  for (wdgtb = 0; ; wdgtb++)
+    {
+      /* WDGTB = 0 -> Divider = 1  = 1 << 0
+       * WDGTB = 1 -> Divider = 2  = 1 << 1
+       * WDGTB = 2 -> Divider = 4  = 1 << 2
+       * WDGTB = 3 -> Divider = 8  = 1 << 3
+       */
+
+      /* Get the WWDG counter frequency in Hz. */
+
+      fwwdg = (STM32_PCLK1_FREQUENCY/4096) >> wdgtb;
+
+      /* The formula to calculate the timeout value is given by:
+       *
+       * timeout =  1000 * (reload + 1) / Fwwdg, OR
+       * reload = timeout * Fwwdg / 1000 - 1
+       *
+       * Where
+       *  timeout is the desired timout in milliseconds
+       *  reload is the contents of T{5:0]
+       *  Fwwdg is the frequency of the WWDG clock
+       */
+
+       reload = timeout * fwwdg / 1000 - 1;
+
+      /* If this reload valid is less than the maximum or we are not ready
+       * at the prescaler value, then break out of the loop to use these
+       * settings.
+       */
+
+      if (reload <= WWDG_CFR_W_MAX || wdgtb == 3)
+        {
+          /* Note that we explicity break out of the loop rather than using
+           * the 'for' loop termination logic because we do not want the
+           * value of wdgtb to be incremented.
+           */
+
+          break;
+        }
+    }
+
+  /* Make sure that the final reload value is within range */
+
+  if (reload > WWDG_CFR_W_MAX)
+    {
+      reload = WWDG_CFR_W_MAX;
+    }
+
+  /* Calculate and save the actual timeout value in milliseconds:
+   *
+   * timeout =  1000 * (reload + 1) / Fwwdg, OR
+   */
+
+  priv->timeout = 1000 * (reload + 1) / fwwdg;
+
+  /* Remember the selected values */
+
+  priv->fwwdg  = fwwdg;
+  priv->reload = reload;
+  
+  /* Set WDGTB[1:0] bits according to calculated value */
+
+  regval = stm32_getreg(STM32_WWDG_CFR);
+  regval &= WWDG_CFR_WDGTB_MASK;
+  regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT;
+  stm32_putreg(regval, STM32_WWDG_CFR);
+
+  /* Reset the 7-bit window value to the maximum value.. essentially disabling
+   * the lower limit of the watchdog reset time.
+   */
+
+  stm32_setwindow(priv, 0x7f);
+  return OK;
 }
 
 /****************************************************************************
@@ -353,10 +580,45 @@ static xcpt_t stm32_capture(FAR struct watchdog_lowerhalf_s *lower,
                             xcpt_t handler)
 {
   FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
+  irqstate_t flags;
+  xcpt_t oldhandler;
+  uint16_t regval;
 
   DEBUGASSERT(priv);
-#warning "Missing logic"
-  return NULL;
+
+  /* Get the old handler return value */
+
+  flags = irqsave();
+  oldhandler = priv->handler;
+
+  /* Save the new handler */
+
+   priv->handler = handler;
+
+  /* Are we attaching or detaching the handler? */
+
+  regval = stm32_getreg(STM32_WWDG_CFR);
+  if (handler)
+    {
+      /* Attaching... Enable the EWI interrupt */
+
+      regval |= WWDG_CFR_EWI;
+      stm32_putreg(regval, STM32_WWDG_CFR);
+ 
+      up_enable_irq(STM32_IRQ_WWDG);
+    }
+  else
+    {
+      /* Detaching... Disable the EWI interrupt */
+
+      regval &= ~WWDG_CFR_EWI;
+      stm32_putreg(regval, STM32_WWDG_CFR);
+
+      up_disable_irq(STM32_IRQ_WWDG);
+    }
+
+  irqrestore(flags);
+  return oldhandler;
 }
 
 /****************************************************************************
@@ -383,10 +645,32 @@ static int stm32_ioctl(FAR struct watchdog_lowerhalf_s *lower, int cmd,
                     unsigned long arg)
 {
   FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)lower;
+  int ret = -ENOTTY;
 
   DEBUGASSERT(priv);
-#warning "Missing logic"
-  return -ENOSYS;
+
+  /* WDIOC_MINTIME: Set the minimum ping time.  If two keepalive ioctls
+   * are received within this time, a reset event will be generated.
+   * Argument: A 32-bit time value in milliseconds.
+   */
+
+  if (cmd == WDIOC_MINTIME)
+    {
+      uint32_t mintime = (uint32_t)arg;
+ 
+      /* The minimum time should be strictly less than the total delay */
+
+      ret = -EINVAL;
+      if (mintime < priv->timeout)
+        {
+          uint32_t window = (priv->timeout - mintime) * priv->fwwdg / 1000 - 1;
+          DEBUGASSERT(window < priv->reload);
+          stm32_setwindow(priv, window | WWDG_CFR_W_RESET);
+          ret = OK;
+        }
+    }
+
+  return ret;
 }
 
 /****************************************************************************
@@ -414,16 +698,47 @@ void stm32_wwdginitialize(FAR const char *devpath)
 {
   FAR struct stm32_lowerhalf_s *priv = &g_wdgdev;
 
+  /* NOTE we assume that clocking to the IWDG has already been provided by
+   * the RCC initialization logic.
+   */
+
   /* Initialize the driver state structure.  Here we assume: (1) the state
-   * structure lies in .bss and was zeroed at reset time.  This function is
-   * only called once so it is never necessary to re-zero the structure.
+   * structure lies in .bss and was zeroed at reset time.  (2) This function
+   * is only called once so it is never necessary to re-zero the structure.
+   */
+
+  priv->ops = &g_wdgops;
+
+  /* Attach our EWI interrupt handler (But don't enable it yet) */
+
+  (void)irq_attach(STM32_IRQ_WWDG, stm32_interrupt);
+
+  /* Select an arbitrary initial timeout value.  But don't start the watchdog
+   * yet. NOTE: If the "Hardware watchdog" feature is enabled through the
+   * device option bits, the watchdog is automatically enabled at power-on.
    */
 
-  priv->ops     = &g_wdgops;
+  stm32_settimeout((FAR struct watchdog_lowerhalf_s *)priv,
+                   CONFIG_STM32_WWDG_DEFTIMOUT);
 
   /* Register the watchdog driver as /dev/watchdog0 */
 
   (void)watchdog_register(devpath, (FAR struct watchdog_lowerhalf_s *)priv);
+
+  /* When the microcontroller enters debug mode (Cortex™-M4F core halted),
+   * the WWDG counter either continues to work normally or stops, depending
+   * on DBG_WWDG_STOP configuration bit in DBG module.
+   */
+
+#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \
+    defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \
+    defined(CONFIG_STM32_JTAG_SW_ENABLE)
+    {
+      uint32_t cr = getreg32(STM32_DBGMCU_CR);
+      cr |= DBGMCU_CR_WWDGSTOP;
+      putreg32(cr, STM32_DBGMCU_CR);
+    }
+#endif
 }
 
 #endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */
diff --git a/nuttx/include/nuttx/watchdog.h b/nuttx/include/nuttx/watchdog.h
index 75e5f4c912..83219caf22 100755
--- a/nuttx/include/nuttx/watchdog.h
+++ b/nuttx/include/nuttx/watchdog.h
@@ -54,6 +54,8 @@
  * transfer interface, the majority of the functionality is implemented in
  * driver ioctl calls.  The watchdog ioctl commands are lised below:
  *
+ * These are detected and handled by the "upper half" watchdog timer driver.
+ *
  * WDIOC_START      - Start the watchdog timer
  *                    Argument: Ignored
  * WDIOC_STOP       - Stop the watchdog timer
@@ -66,6 +68,14 @@
  *                    Argument: A pointer to struct watchdog_capture_s.
  * WDIOC_KEEPALIVE  - Reset the watchdog timer ("ping", "pet the dog");
  *                    Argument: Ignored
+ *
+ * These may be supported by certain "lower half" drivers
+ *
+ * WDIOC_MINTIME    - Set the minimum ping time.  If two keepalive ioctls
+ *                    are received within this time, a reset event will
+ *                    be generated.  This feature should assume to be 
+ *                    disabled after WDIOC_SETTIMEOUT.
+ *                    Argument: A 32-bit time value in milliseconds.
  */
 
 #define WDIOC_START      _WDIOC(0x001)
@@ -75,6 +85,8 @@
 #define WDIOC_CAPTURE    _WDIOC(0x005)
 #define WDIOC_KEEPALIVE  _WDIOC(0x006)
 
+#define WDIOC_MINTIME    _WDIOC(0x080)
+
 /* Bit Settings *************************************************************/
 /* Bit settings for the struct watchdog_status_s flags field */