diff options
Diffstat (limited to 'tests/rlcmac/rlcmac_prim_test.ok')
| -rw-r--r-- | tests/rlcmac/rlcmac_prim_test.ok | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/tests/rlcmac/rlcmac_prim_test.ok b/tests/rlcmac/rlcmac_prim_test.ok index 0c66e24..dcaa816 100644 --- a/tests/rlcmac/rlcmac_prim_test.ok +++ b/tests/rlcmac/rlcmac_prim_test.ok @@ -1,6 +1,6 @@ === test_ul_tbf_attach start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7e +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 @@ -14,21 +14,21 @@ sys={0.027690}, mono={0.027690}: Expect defer_pkt_idle_timer timeout test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request === test_ul_tbf_t3164_timeout start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x79 +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 sys={5.000000}, mono={5.000000}: clock_override_add sys={5.000000}, mono={5.000000}: Expect T3164 timeout test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 sys={10.000000}, mono={10.000000}: clock_override_add sys={10.000000}, mono={10.000000}: Expect T3164 timeout test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x79 +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 sys={15.000000}, mono={15.000000}: clock_override_add @@ -47,7 +47,7 @@ sys={20.027690}, mono={20.027690}: Expect defer_pkt_idle_timer timeout test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request === test_ul_tbf_t3166_timeout start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7a +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 @@ -56,7 +56,7 @@ sys={5.000000}, mono={5.000000}: clock_override_add sys={5.000000}, mono={5.000000}: Expect T3166 timeout test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7c +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ] @@ -64,7 +64,7 @@ sys={10.000000}, mono={10.000000}: clock_override_add sys={10.000000}, mono={10.000000}: Expect T3166 timeout test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x79 +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ] @@ -72,7 +72,7 @@ sys={15.000000}, mono={15.000000}: clock_override_add sys={15.000000}, mono={15.000000}: Expect T3166 timeout test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7d +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ] @@ -85,7 +85,7 @@ sys={20.027690}, mono={20.027690}: Expect defer_pkt_idle_timer timeout test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request === test_ul_tbf_n3104_timeout start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7a +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 RTS 0: FN=8 @@ -115,7 +115,7 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=52 ts=7 data_len=34 da RTS 11: FN=56 test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=56 ts=7 data_len=34 data=[00 01 04 3d 00 00 23 42 71 62 f2 24 6c 84 44 04 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ] test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 @@ -123,7 +123,7 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask= test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 === test_ul_tbf_t3182_timeout start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7a +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 @@ -138,7 +138,7 @@ sys={5.027690}, mono={5.027690}: Expect defer_pkt_idle_timer timeout test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request === test_ul_tbf_last_data_cv0_retrans_max start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 @@ -159,7 +159,7 @@ sys={0.027690}, mono={0.027690}: Expect defer_pkt_idle_timer timeout test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request === test_ul_tbf_countdown_procedure start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7b +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 @@ -180,7 +180,7 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=30 ts=7 data_len=34 da test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 === test_ul_tbf_request_another_ul_tbf start === sys={0.000000}, mono={0.000000}: clock_override_set -test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x7e +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 |