diff options
Diffstat (limited to 'tests/rlcmac/rlcmac_prim_test.ok')
| -rw-r--r-- | tests/rlcmac/rlcmac_prim_test.ok | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/rlcmac/rlcmac_prim_test.ok b/tests/rlcmac/rlcmac_prim_test.ok index 571f918..70d0939 100644 --- a/tests/rlcmac/rlcmac_prim_test.ok +++ b/tests/rlcmac/rlcmac_prim_test.ok @@ -91,6 +91,21 @@ test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask= sys={20.027690}, mono={20.027690}: clock_override_add sys={20.027690}, mono={20.027690}: Expect defer_pkt_idle_timer timeout test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request +=== test_ul_tbf_t3180_timeout start === +sys={0.000000}, mono={0.000000}: clock_override_set +test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 +test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_ESTABLISH.request +test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x80 +test_rlcmac_prim_up_cb(): Rx GMMRR-LLC_TRANSMITTED.indication TLLI=0x00002342 +test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=4 ts=7 data_len=34 data=[3c 01 01 00 00 23 42 01 c0 00 08 01 01 d5 71 00 00 08 29 26 24 00 00 00 00 71 62 f2 24 6c 84 44 04 00 ] +test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_DATA.request fn=8 ts=7 data_len=34 data=[00 01 02 1d 00 00 23 42 11 e5 10 00 e2 18 f2 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 00 ] +sys={5.000000}, mono={5.000000}: clock_override_add +sys={5.000000}, mono={5.000000}: Expect T3180 timeout +test_rlcmac_prim_down_cb(): Rx L1CTL-CFG_UL_TBF.request ul_tbf_nr=0 ul_slotmask=0x00 +=== test_ul_tbf_t3180_timeout end === +sys={5.027690}, mono={5.027690}: clock_override_add +sys={5.027690}, mono={5.027690}: Expect defer_pkt_idle_timer timeout +test_rlcmac_prim_down_cb(): Rx L1CTL-PDCH_RELEASE.request === test_ul_tbf_n3104_timeout start === sys={0.000000}, mono={0.000000}: clock_override_set test_rlcmac_prim_down_cb(): Rx L1CTL-RACH.request ra=0x78 |