Clean up a bunch of stuff.

The command byte values aren't FPGA-specific - if they were, the code
wouldn't have worked.  Provide #defines for the main ones and check for
them, and use that to determine whether the packet is transmitted or
received.

Add a bunch of #defines, shuffle some defines to cluster related ones
together and separate unrelated ones, get rid of duplicate #defines
(where different FPGAs use the same value).

Fix some typoes.

Change-Id: Ic8adc589d7c36a4a91a81858de40c904743dd067
Reviewed-on: https://code.wireshark.org/review/9529
Reviewed-by: Guy Harris <guy@alum.mit.edu>

1 files changed, 157 insertions, 99 deletions

diff --git a/wiretap/vwr.c b/wiretap/vwr.c
index 833bebc114..2cc55f01b5 100644
--- a/wiretap/vwr.c
+++ b/wiretap/vwr.c
@@ -72,15 +72,19 @@
  * A record begins with a 16-byte header, the first 8 bytes of which
  * begin with a byte containing a command plus transmit-receive flags.
  *
- * Following that are two big-endian 32-bi quantities; for some records
+ * Following that are two big-endian 32-bit quantities; for some records
  * one or the other of them is the length of the rest of the record.
  * Other records contain only the header.
  */
 #define VW_RECORD_HEADER_LENGTH 16
 
+/* Command byte values */
+#define COMMAND_RX  0x21
+#define COMMAND_TX  0x31
+
 /* the metadata headers */
 
-/* Size of thhe IxVeriwave common header */
+/* Size of the IxVeriwave common header */
 #define STATS_COMMON_FIELDS_LEN (2+2+2+4+2+2+4+4+8+8+4)
 
 /* For VeriWave WLAN and Ethernet metadata headers vw_flags field */
@@ -140,7 +144,7 @@
 #define v22_E_INFO_OFF           40                 /* NO INFO FIELD IN ETHERNET STATS! */
 #define v22_E_DIFFERENTIATOR_OFF  0                 /* offset to determine whether */
                                                     /* eth/802.11, 8 bits */
-
+/* Media types */
 #define v22_E_MT_10_HALF    0                       /* 10 Mb/s half-duplex */
 #define v22_E_MT_10_FULL    1                       /* 10 Mb/s full-duplex */
 #define v22_E_MT_100_HALF   2                       /* 100 Mb/s half-duplex */
@@ -148,20 +152,29 @@
 #define v22_E_MT_1G_HALF    4                       /* 1 Gb/s half-duplex */
 #define v22_E_MT_1G_FULL    5                       /* 1 Gb/s full-duplex */
 
+/* Error flags */
 #define v22_E_FCS_ERROR           0x0002            /* FCS error flag in error vector */
 #define v22_E_CRYPTO_ERR          0x1f00            /* RX decrypt error flags (UNUSED) */
 #define v22_E_SIG_ERR             0x0004            /* signature magic byte mismatch */
 #define v22_E_PAYCHK_ERR          0x0008            /* payload checksum failure */
 #define v22_E_RETRY_ERR           0x0400            /* excessive retries on TX fail (UNUSED)*/
+
+/* Masks and defines */
 #define v22_E_IS_RX               0x08              /* TX/RX bit in STATS block */
 #define v22_E_MT_MASK             0x07              /* modulation type mask (UNUSED) */
-#define v22_E_VCID_MASK           0x03ff            /* VC ID is only 9 bits */
+
+#define v22_E_VCID_MASK           0x03ff            /* VC ID is only 10 bits */
+
 #define v22_E_FLOW_VALID          0x40              /* flow-is-valid flag (else force to 0) */
+
 #define v22_E_DIFFERENTIATOR_MASK 0X3F              /* mask to differentiate ethernet from */
-#define v22_E_IS_TCP              0x00000040        /* TCP bit in FRAME_TYPE field */
-#define v22_E_IS_UDP              0x00000010        /* UDP bit in FRAME_TYPE field */
-#define v22_E_IS_ICMP             0x00000020        /* ICMP bit in FRAME_TYPE field */
-#define v22_E_IS_IGMP             0x00000080        /* IGMP bit in FRAME_TYPE field */
+
+/* Bits in FRAME_TYPE field */
+#define v22_E_IS_TCP              0x00000040        /* TCP */
+#define v22_E_IS_UDP              0x00000010        /* UDP */
+#define v22_E_IS_ICMP             0x00000020        /* ICMP */
+#define v22_E_IS_IGMP             0x00000080        /* IGMP */
+
 #define v22_E_IS_QOS              0x80              /* QoS bit in MTYPE field (WLAN only) */
 #define v22_E_IS_VLAN             0x00200000
 
@@ -171,10 +184,6 @@
 
 #define v22_E_FC_PROT_BIT   0x40                    /* Protected Frame bit in FC1 of frame */
 
-
-#define v22_E_HEADER_IS_RX  0x21
-#define v22_E_HEADER_IS_TX  0x31
-
 #define v22_E_IS_ETHERNET   0x00700000              /* bits set in frame type if ethernet */
 #define v22_E_IS_80211      0x7F000000              /* bits set in frame type if 802.11 */
 
@@ -202,38 +211,60 @@
 #define v22_W_PLCP_LENGTH_OFF     4                 /* LENGTH field in the plcp header */
 
 
+/* Modulation types */
 #define v22_W_MT_CCKL       0                       /* CCK modulation, long preamble */
 #define v22_W_MT_CCKS       1                       /* CCK modulation, short preamble */
 #define v22_W_MT_OFDM       2                       /* OFDM modulation */
 
-#define v22_W_IS_TCP            0x00000040                  /* TCP bit in FRAME_TYPE field */
-#define v22_W_IS_UDP            0x00000010                  /* UDP bit in FRAME_TYPE field */
-#define v22_W_IS_ICMP           0x00000020                  /* ICMP bit in FRAME_TYPE field */
-#define v22_W_IS_IGMP           0x00000080                  /* IGMP bit in FRAME_TYPE field */
-#define v22_W_IS_QOS            0x80                        /* QoS bit in MTYPE field (WLAN only) */
+/* Bits in FRAME_TYPE field */
+#define v22_W_IS_TCP            0x00000040                  /* TCP */
+#define v22_W_IS_UDP            0x00000010                  /* UDP */
+#define v22_W_IS_ICMP           0x00000020                  /* ICMP */
+#define v22_W_IS_IGMP           0x00000080                  /* IGMP */
 
+/* Bits in MTYPE field (WLAN only) */
+#define v22_W_IS_QOS            0x80                        /* QoS */
 
+/* Error flags */
 #define v22_W_FCS_ERROR     0x0002                  /* FCS error flag in error vector */
 #define v22_W_CRYPTO_ERR    0x1f00                  /* RX decrypt error flags */
 #define v22_W_SIG_ERR       0x0004                  /* signature magic byte mismatch */
 #define v22_W_PAYCHK_ERR    0x0008                  /* payload checksum failure */
 #define v22_W_RETRY_ERR     0x0400                  /* excessive retries on TX failure */
+
+/* Masks and defines */
 #define v22_W_IS_RX         0x08                    /* TX/RX bit in STATS block */
 #define v22_W_MT_MASK       0x07                    /* modulation type mask */
+
 #define v22_W_VCID_MASK     0x01ff                  /* VC ID is only 9 bits */
+
 #define v22_W_FLOW_VALID    0x40                    /* flow-is-valid flag (else force to 0) */
+
 #define v22_W_DIFFERENTIATOR_MASK 0Xf0ff            /* mask to differentiate ethernet from */
                                                     /* 802.11 capture */
 
 #define v22_W_RX_DECRYPTS   0x0007                  /* RX-frame-was-decrypted bits */
 #define v22_W_TX_DECRYPTS   0x0007                  /* TX-frame-was-decrypted bits */
 
-#define v22_W_WEPTYPE       0x0001                  /* WEP frame */
-#define v22_W_TKIPTYPE      0x0002                  /* TKIP frame */
-#define v22_W_CCMPTYPE      0x0004                  /* CCMP frame */
-
-#define v22_W_HEADER_IS_RX  0x21
-#define v22_W_HEADER_IS_TX  0x31
+/* Info bits */
+#define v22_W_WEPTYPE               0x0001          /* WEP frame */
+#define v22_W_TKIPTYPE              0x0002          /* TKIP frame */
+#define v22_W_CCMPTYPE              0x0004          /* CCMP frame */
+#define v22_W_MPDU_OF_A_MPDU        0x0400          /* MPDU of A-MPDU */
+#define v22_W_FIRST_MPDU_OF_A_MPDU  0x0800          /* first MPDU of A-MPDU */
+#define v22_W_LAST_MPDU_OF_A_MPDU   0x1000          /* last MPDU of A-MPDU */
+#define v22_W_MSDU_OF_A_MSDU        0x2000          /* MSDU of A-MSDU */
+#define v22_W_FIRST_MSDU_OF_A_MSDU  0x4000          /* first MSDU of A-MSDU */
+#define v22_W_LAST_MSDU_OF_A_MSDU   0x8000          /* last MSDU of A-MSDU */
+
+/* All aggregation flags */
+#define v22_W_AGGREGATE_FLAGS \
+    (v22_W_MPDU_OF_A_MPDU | \
+     v22_W_FIRST_MPDU_OF_A_MPDU | \
+     v22_W_LAST_MPDU_OF_A_MPDU | \
+     v22_W_MSDU_OF_A_MSDU | \
+     v22_W_FIRST_MSDU_OF_A_MSDU | \
+     v22_W_LAST_MSDU_OF_A_MSDU)
 
 #define v22_W_FC_PROT_BIT   0x40                    /* Protected Frame bit in FC1 of frame */
 
@@ -292,28 +323,66 @@
 #define vVW510021_W_QOS_VALID           0x4000
 #define vVW510021_W_HT_VALID            0x2000
 #define vVW510021_W_L4ID_VALID          0x1000
-#define vVW510021_W_PREAMBLE_MASK       0x40        /* short/long preamble/guard(ofdm) mask */
-#define vVW510021_W_MCS_MASK            0x3f        /* mcs index (a/b) type mask */
 #define vVW510021_W_MOD_SCHEME_MASK     0x3f        /* modulation type mask */
-#define vVW510021_W_PLCPC_MASK          0x03        /* PLPCP type mask */
 #define vVW510021_W_SEL_MASK            0x80
 #define vVW510021_W_WEP_MASK            0x0001
 #define vVW510021_W_CBW_MASK            0xC0
 
+#define vVW510024_W_VCID_MASK           0x03ff      /* VC ID is only 10 bits */
+
 #define vVW510021_W_MT_SEL_LEGACY       0x00
-#define vVW510021_W_PLCP_LEGACY         0x00
-#define vVW510021_W_PLCP_MIXED          0x01
-#define vVW510021_W_PLCP_GREENFIELD     0x02
-#define vVW510021_W_PLCP_VHT_MIXED      0x03
-#define vVW510021_W_HEADER_IS_RX        0x21
-#define vVW510021_W_HEADER_IS_TX        0x31
+
 #define vVW510021_W_IS_WEP              0x0001
-#define vVW510021_W_IS_LONGPREAMBLE     0x40
 
-#define vVW510021_W_IS_TCP          0x01000000                  /* TCP bit in FRAME_TYPE field */
-#define vVW510021_W_IS_UDP          0x00100000                  /* UDP bit in FRAME_TYPE field */
-#define vVW510021_W_IS_ICMP         0x00001000                  /* ICMP bit in FRAME_TYPE field */
-#define vVW510021_W_IS_IGMP         0x00010000                  /* IGMP bit in FRAME_TYPE field */
+/* L1p byte 1 info */
+
+/* Common to Series II and Series III */
+
+#define vVW510021_W_IS_LONGPREAMBLE     0x40        /* short/long preamble bit */
+#define vVW510021_W_IS_LONGGI           0x40        /* short/long guard interval bit */
+
+/* Series II */
+
+#define vVW510021_W_S2_MCS_INDEX(l1p_1) ((l1p_1) & 0x3f) /* MCS index */
+
+/* Series III */
+
+/*
+ * VHT - contains MCS index and number of spatial streams.
+ * The number of spatial streams from the FPGA is zero-based, so we add
+ * 1 to it.
+ */
+#define vVW510021_W_S3_MCS_INDEX_VHT(l1p_1) ((l1p_1) & 0x0f) /* MCS index */
+#define vVW510021_W_S3_NSS_VHT(l1p_1)       (((l1p_1) >> 4 & 0x3) + 1) /* NSS */
+
+/*
+ * HT - contains MCS index
+ */
+#define vVW510021_W_S3_MCS_INDEX_HT(l1p_1)  ((l1p_1) & 0x3f)
+
+/* L1p byte 2 info */
+
+/* Common to Series II and Series III */
+#define vVW510021_W_BANDWIDTH_VHT(l1p_2) (((l1p_2) >> 4) & 0xf)
+/* 3 = 40 MHz, 4 = 80 MHz; what about 20 and 160 MHz? */
+
+/* Series II */
+#define vVW510021_W_S2_PLCP_TYPE(l1p_2) ((l1p_2) & 0x03) /* PLCP type */
+
+/* Series III */
+#define vVW510021_W_S3_PLCP_TYPE(l1p_2) ((l1p_2) & 0x0f) /* PLCP type */
+
+/* PLCP types */
+#define vVW510021_W_PLCP_LEGACY         0x00        /* pre-HT (11b/a/g) */
+#define vVW510021_W_PLCP_MIXED          0x01        /* HT, mixed (11n) */
+#define vVW510021_W_PLCP_GREENFIELD     0x02        /* HT, greenfield (11n) */
+#define vVW510021_W_PLCP_VHT_MIXED      0x03        /* VHT (11ac) */
+
+/* Bits in FRAME_TYPE field */
+#define vVW510021_W_IS_TCP          0x01000000      /* TCP */
+#define vVW510021_W_IS_UDP          0x00100000      /* UDP */
+#define vVW510021_W_IS_ICMP         0x00001000      /* ICMP */
+#define vVW510021_W_IS_IGMP         0x00010000      /* IGMP */
 
 
 #define vVW510021_W_HEADER_VERSION      0x00
@@ -322,13 +391,12 @@
 #define S2_W_FPGA_VERSION               0x000C
 #define vVW510021_W_11n_FPGA_VERSION    0x000D
 
-/* Error masks */
+/* Error flags */
 #define vVW510021_W_FCS_ERROR           0x01
+
 #define vVW510021_W_CRYPTO_ERROR        0x50000
 
-#define vVW510021_W_WEPTYPE             0x0001      /* WEP frame */
-#define vVW510021_W_TKIPTYPE            0x0002      /* TKIP frame */
-#define vVW510021_W_CCMPTYPE            0x0004      /* CCMP frame */
+/* Info bits are the same as for the VWS10006 FPGA */
 
 /* definitions for VW510024 FPGA, wired ethernet format */
 /* FORMAT:
@@ -369,10 +437,8 @@
 #define vVW510024_E_QOS_VALID           0x0000                  /** not valid for ethernet **/
 #define vVW510024_E_L4ID_VALID          0x1000
 #define vVW510024_E_CBW_MASK            0xC0
-#define vVW510024_E_VCID_MASK           0x3FFF
 
-#define vVW510024_E_HEADER_IS_RX        0x21
-#define vVW510024_E_HEADER_IS_TX        0x31
+#define vVW510024_E_VCID_MASK           0x3fff                  /* VCID is only 14 bits */
 
 #define vVW510024_E_IS_TCP          0x01000000                  /* TCP bit in FRAME_TYPE field */
 #define vVW510024_E_IS_UDP          0x00100000                  /* UDP bit in FRAME_TYPE field */
@@ -464,7 +530,7 @@ typedef struct {
     guint32      RETRY_ERR;                      /* excessive retries on TX failure */
     guint8       IS_RX;                          /* TX/RX bit in STATS block */
     guint8       MT_MASK;                        /* modulation type mask */
-    guint16      VCID_MASK;                      /* VC ID is only 9 bits */
+    guint16      VCID_MASK;                      /* VC ID might not be a full 16 bits */
     guint32      FLOW_VALID;                     /* flow-is-valid flag (else force to 0) */
     guint16      QOS_VALID;
     guint32      RX_DECRYPTS;                    /* RX-frame-was-decrypted bits */
@@ -473,10 +539,7 @@ typedef struct {
     guint32      MT_CCKL;                        /* CCK modulation, long preamble */
     guint32      MT_CCKS;                        /* CCK modulation, short preamble */
     guint32      MT_OFDM;                        /* OFDM modulation */
-    guint32      MCS_INDEX_MASK;                 /* mcs index type mask */
     guint32      FPGA_VERSION;
-    guint32      HEADER_IS_RX;
-    guint32      HEADER_IS_TX;
     guint32      WEPTYPE;                        /* frame is WEP */
     guint32      TKIPTYPE;                       /* frame is TKIP */
     guint32      CCMPTYPE;                       /* frame is CCMP */
@@ -490,7 +553,7 @@ typedef struct {
 } vwr_t;
 
 /* internal utility functions */
-static int          decode_msg(vwr_t *vwr, register guint8 *, int *, int *);
+static int          decode_msg(register guint8 *, int *, int *);
 static guint8       get_ofdm_rate(const guint8 *);
 static guint8       get_cck_rate(const guint8 *plcp);
 static void         setup_defaults(vwr_t *, guint16);
@@ -499,7 +562,7 @@ static gboolean     vwr_read(wtap *, int *, gchar **, gint64 *);
 static gboolean     vwr_seek_read(wtap *, gint64, struct wtap_pkthdr *phdr,
                                   Buffer *, int *, gchar **);
 
-static gboolean     vwr_read_rec_header(vwr_t *, FILE_T, int *, int *, int *, gchar **);
+static gboolean     vwr_read_rec_header(FILE_T, int *, int *, int *, gchar **);
 static gboolean     vwr_process_rec_data(FILE_T fh, int rec_size,
                                          struct wtap_pkthdr *phdr, Buffer *buf,
                                          vwr_t *vwr, int IS_TX, int *err,
@@ -576,7 +639,7 @@ static gboolean vwr_read(wtap *wth, int *err, gchar **err_info, gint64 *data_off
     int    rec_size = 0, IS_TX;
 
     /* read the next frame record header in the capture file; if no more frames, return */
-    if (!vwr_read_rec_header(vwr, wth->fh, &rec_size, &IS_TX, err, err_info))
+    if (!vwr_read_rec_header(wth->fh, &rec_size, &IS_TX, err, err_info))
         return FALSE;                                   /* Read error or EOF */
 
     /*
@@ -617,7 +680,7 @@ static gboolean vwr_seek_read(wtap *wth, gint64 seek_off,
         return FALSE;
 
     /* read in the record header */
-    if (!vwr_read_rec_header(vwr, wth->random_fh, &rec_size, &IS_TX, err, err_info))
+    if (!vwr_read_rec_header(wth->random_fh, &rec_size, &IS_TX, err, err_info))
         return FALSE;                                  /* Read error or EOF */
 
     return vwr_process_rec_data(wth->random_fh, rec_size, phdr, buf,
@@ -629,7 +692,7 @@ static gboolean vwr_seek_read(wtap *wth, gint64 seek_off,
 /* Return TRUE on success, FALSE on EOF or error.                           */
 /* Also return the frame size in bytes and the "is transmitted frame" flag. */
 
-static gboolean vwr_read_rec_header(vwr_t *vwr, FILE_T fh, int *rec_size, int *IS_TX, int *err, gchar **err_info)
+static gboolean vwr_read_rec_header(FILE_T fh, int *rec_size, int *IS_TX, int *err, gchar **err_info)
 {
     int     f_len, v_type;
     guint8  header[VW_RECORD_HEADER_LENGTH];
@@ -649,7 +712,7 @@ static gboolean vwr_read_rec_header(vwr_t *vwr, FILE_T fh, int *rec_size, int *I
         /* If the function returns a length, then a frame or variable-length message */
         /*  follows the 16-byte message.                                             */
         /* If the variable length message is not a frame, simply skip over it.       */
-        if ((f_len = decode_msg(vwr, header, &v_type, IS_TX)) != 0) {
+        if ((f_len = decode_msg(header, &v_type, IS_TX)) != 0) {
             if (f_len > B_SIZE) {
                 *err = WTAP_ERR_BAD_FILE;
                 *err_info = g_strdup_printf("vwr: Invalid message record length %d", f_len);
@@ -706,7 +769,7 @@ static int vwr_get_fpga_version(wtap *wth, int *err, gchar **err_info)
         /* If the function returns a length, then a frame or variable-length message */
         /*  follows the 16-byte message.                                             */
         /* If the variable length message is not a frame, simply skip over it.       */
-        if ((f_len = decode_msg(NULL, header, &v_type, NULL)) != 0) {
+        if ((f_len = decode_msg(header, &v_type, NULL)) != 0) {
             if (f_len > B_SIZE) {
                 /* Treat this here as an indication that the file probably */
                 /*  isn't a vwr file. */
@@ -1140,8 +1203,8 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
     l1p_2 = s_start_ptr[vVW510021_W_L1P_2_OFF];
     if (vwr->FPGA_VERSION == S2_W_FPGA)
     {
-        mcs_index = l1p_1 & 0x3f;
-        plcp_type = l1p_2 & 0x03;
+        mcs_index = vVW510021_W_S2_MCS_INDEX(l1p_1);
+        plcp_type = vVW510021_W_S2_PLCP_TYPE(l1p_2);
         /* we do the range checks at the end before copying the values
            into the wtap header */
         msdu_length = ((s_start_ptr[vVW510021_W_MSDU_LENGTH_OFF+1] & 0x1f) << 8)
@@ -1169,19 +1232,21 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
     }
     else
     {
-        plcp_type = l1p_2 & 0xf;
+        plcp_type = vVW510021_W_S3_PLCP_TYPE(l1p_2);
         if (plcp_type == vVW510021_W_PLCP_VHT_MIXED)
         {
-            mcs_index = l1p_1 & 0x0f;
-            nss = (l1p_1 >> 4 & 0x3) + 1; /* The nss is zero based from the fpga - increment it here */
+            /* VHT */
+            mcs_index = vVW510021_W_S3_MCS_INDEX_VHT(l1p_1);
+            nss = vVW510021_W_S3_NSS_VHT(l1p_1);
         }
         else
         {
-            mcs_index = l1p_1 & 0x3f;
+            /* HT */
+            mcs_index = vVW510021_W_S3_MCS_INDEX_HT(l1p_1);
             nss = 0;
         }
         msdu_length = pntoh24(&s_start_ptr[9]);
-        vc_id = pntoh16(&s_start_ptr[14]) & 0x3ff;
+        vc_id = pntoh16(&s_start_ptr[14]) & vVW510024_W_VCID_MASK;
         for (i = 0; i < 4; i++)
         {
             if (IS_TX)
@@ -1224,7 +1289,7 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
 
     errors = pntoh32(&s_trail_ptr[vVW510021_W_ERRORS_OFF]);
     info = pntoh16(&s_trail_ptr[vVW510021_W_INFO_OFF]);
-    if ((info & 0xFC00) != 0)
+    if ((info & v22_W_AGGREGATE_FLAGS) != 0)
     /* this length includes the Start_Spacing + Delimiter + MPDU + Padding for each piece of the aggregate*/
         ht_len = pletoh16(&s_start_ptr[vwr->PLCP_LENGTH_OFF]);
 
@@ -1242,18 +1307,18 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
     else if (plcp_type == vVW510021_W_PLCP_MIXED) {
         /* set the appropriate flags to indicate HT mode and CB */
         radioflags |= FLAGS_CHAN_HT | ((plcp_ptr[3] & 0x80) ? FLAGS_CHAN_40MHZ : 0) |
-                      ((l1p_1 & 0x40) ? 0 : FLAGS_CHAN_SHORTGI);
+                      ((l1p_1 & vVW510021_W_IS_LONGGI) ? 0 : FLAGS_CHAN_SHORTGI);
         chanflags  |= CHAN_OFDM;
     }
     else if (plcp_type == vVW510021_W_PLCP_GREENFIELD) {
         /* set the appropriate flags to indicate HT mode and CB */
         radioflags |= FLAGS_CHAN_HT | ((plcp_ptr[0] & 0x80) ? FLAGS_CHAN_40MHZ : 0) |
-                      ((l1p_1 & 0x40) ?  0 : FLAGS_CHAN_SHORTGI);
+                      ((l1p_1 & vVW510021_W_IS_LONGGI) ?  0 : FLAGS_CHAN_SHORTGI);
         chanflags  |= CHAN_OFDM;
     }
     else if (plcp_type == vVW510021_W_PLCP_VHT_MIXED) {
-        guint8 SBW = l1p_2 >> 4 & 0xf;
-        radioflags |= FLAGS_CHAN_VHT | ((l1p_1 & 0x40) ?  0 : FLAGS_CHAN_SHORTGI);
+        guint8 SBW = vVW510021_W_BANDWIDTH_VHT(l1p_2);
+        radioflags |= FLAGS_CHAN_VHT | ((l1p_1 & vVW510021_W_IS_LONGGI) ?  0 : FLAGS_CHAN_SHORTGI);
         chanflags |= CHAN_OFDM;
         if (SBW == 3)
             radioflags |= FLAGS_CHAN_40MHZ;
@@ -1378,7 +1443,7 @@ static gboolean vwr_read_s2_W_rec(vwr_t *vwr, struct wtap_pkthdr *phdr,
     bytes_written += 2;
     if (info & vVW510021_W_IS_WEP)
         radioflags |= FLAGS_WEP;
-    if ((l1p_1 & vVW510021_W_PREAMBLE_MASK) != vVW510021_W_IS_LONGPREAMBLE && (plcp_type == vVW510021_W_PLCP_LEGACY))
+    if (!(l1p_1 & vVW510021_W_IS_LONGPREAMBLE) && (plcp_type == vVW510021_W_PLCP_LEGACY))
         radioflags |= FLAGS_SHORTPRE;
     phtoles(&data_ptr[bytes_written], radioflags);
     bytes_written += 2;
@@ -1703,7 +1768,7 @@ static gboolean vwr_read_rec_data_ethernet(vwr_t *vwr, struct wtap_pkthdr *phdr,
 /*--------------------------------------------------------------------------------------*/
 /* utility to split up and decode a 16-byte message record */
 
-static int decode_msg(vwr_t *vwr, guint8 *rec, int *v_type, int *IS_TX)
+static int decode_msg(guint8 *rec, int *v_type, int *IS_TX)
 {
     guint8  cmd;                        /* components of message */
     guint32 wd2, wd3;
@@ -1711,37 +1776,44 @@ static int decode_msg(vwr_t *vwr, guint8 *rec, int *v_type, int *IS_TX)
                                         /* assume it's zero */
 
     /* break up the message record into its pieces */
-    cmd = rec[0];
-    wd2 = pntoh32(&rec[8]);
-    wd3 = pntoh32(&rec[12]);
-
-    if (vwr != NULL) {
-        if ((cmd & vwr->HEADER_IS_TX) == vwr->HEADER_IS_TX)
-            *IS_TX = 1;
-        else if ((cmd & vwr->HEADER_IS_RX) == vwr->HEADER_IS_RX)
-            *IS_TX = 0;
-        else *IS_TX = 2; /*NULL case*/
-    }
+    cmd = rec[0];            /* command byte */
+    wd2 = pntoh32(&rec[8]);  /* first 32-bit quantity */
+    wd3 = pntoh32(&rec[12]); /* second 32-bit quantity */
+
     /* now decode based on the command byte */
     switch (cmd) {
-        case 0x21:
-        case 0x31:
+        case COMMAND_RX:
+            if (IS_TX != NULL)
+                *IS_TX = 0;
+            v_size  = (int)(wd2 & 0xffff);
+            *v_type = VT_FRAME;
+            break;
+
+        case COMMAND_TX:
+            if (IS_TX != NULL)
+                *IS_TX = 1;
             v_size  = (int)(wd2 & 0xffff);
             *v_type = VT_FRAME;
             break;
 
         case 0xc1:
         case 0x8b:
+            if (IS_TX != NULL)
+                *IS_TX = 2; /*NULL case*/
             v_size  = (int)(wd2 & 0xffff);
             *v_type = VT_CPMSG;
             break;
 
         case 0xfe:
+            if (IS_TX != NULL)
+                *IS_TX = 2; /*NULL case*/
             v_size  = (int)(wd3 & 0xffff);
             *v_type = VT_CPMSG;
             break;
 
         default:
+            if (IS_TX != NULL)
+                *IS_TX = 2; /*NULL case*/
             break;
     }
 
@@ -1817,10 +1889,7 @@ static void setup_defaults(vwr_t *vwr, guint16 fpga)
             vwr->IPLEN_OFF          = vVW510021_W_IPLEN_OFF;
             vwr->PLCP_LENGTH_OFF    = vVW510021_W_PLCP_LENGTH_OFF;
 
-            vwr->HEADER_IS_RX       = vVW510021_W_HEADER_IS_RX;
-            vwr->HEADER_IS_TX       = vVW510021_W_HEADER_IS_TX;
             vwr->MT_MASK            = vVW510021_W_SEL_MASK;
-            vwr->MCS_INDEX_MASK     = vVW510021_W_MCS_MASK;
             vwr->VCID_MASK          = 0xffff;
             vwr->FLOW_VALID         = vVW510021_W_FLOW_VALID;
             vwr->STATS_START_OFF    = vVW510021_W_HEADER_LEN;
@@ -1842,9 +1911,9 @@ static void setup_defaults(vwr_t *vwr, guint16 fpga)
             vwr->MT_CCKS            = v22_W_MT_CCKS;
             /*vwr->MT_OFDM          = vVW510021_W_MT_OFDM;*/
 
-            vwr->WEPTYPE            = vVW510021_W_WEPTYPE;
-            vwr->TKIPTYPE           = vVW510021_W_TKIPTYPE;
-            vwr->CCMPTYPE           = vVW510021_W_CCMPTYPE;
+            vwr->WEPTYPE            = v22_W_WEPTYPE;
+            vwr->TKIPTYPE           = v22_W_TKIPTYPE;
+            vwr->CCMPTYPE           = v22_W_CCMPTYPE;
 
             vwr->FRAME_TYPE_OFF     =   vVW510021_W_FRAME_TYPE_OFF;
             vwr->IS_TCP             =   vVW510021_W_IS_TCP;
@@ -1864,8 +1933,6 @@ static void setup_defaults(vwr_t *vwr, guint16 fpga)
         case S3_W_FPGA:
             vwr->STATS_LEN       = vVW510021_W_STATS_TRAILER_LEN;
             vwr->PLCP_LENGTH_OFF = 16;
-            vwr->HEADER_IS_RX    = vVW510021_W_HEADER_IS_RX;
-            vwr->HEADER_IS_TX    = vVW510021_W_HEADER_IS_TX;
 
             /*
              * The 8 is from the 16 bytes of stats block that precede the
@@ -1893,9 +1960,6 @@ static void setup_defaults(vwr_t *vwr, guint16 fpga)
             vwr->INFO_OFF       = v22_E_INFO_OFF;
             vwr->L4ID_OFF       = v22_E_L4ID_OFF;
 
-            vwr->HEADER_IS_RX   = v22_E_HEADER_IS_RX;
-            vwr->HEADER_IS_TX   = v22_E_HEADER_IS_TX;
-
             vwr->IS_RX          = v22_E_IS_RX;
             vwr->MT_MASK        = v22_E_MT_MASK;
             vwr->VCID_MASK      = v22_E_VCID_MASK;
@@ -1956,9 +2020,6 @@ static void setup_defaults(vwr_t *vwr, guint16 fpga)
             vwr->VCID_MASK          = v22_W_VCID_MASK;
             vwr->FLOW_VALID         = v22_W_FLOW_VALID;
 
-            vwr->HEADER_IS_RX       = v22_W_HEADER_IS_RX;
-            vwr->HEADER_IS_TX       = v22_W_HEADER_IS_TX;
-
             vwr->RX_DECRYPTS        = v22_W_RX_DECRYPTS;
             vwr->TX_DECRYPTS        = v22_W_TX_DECRYPTS;
             vwr->FC_PROT_BIT        = v22_W_FC_PROT_BIT;
@@ -2007,9 +2068,6 @@ static void setup_defaults(vwr_t *vwr, guint16 fpga)
             vwr->FPGA_VERSION_OFF   = vVW510024_E_FPGA_VERSION_OFF;
             vwr->HEADER_VERSION_OFF = vVW510024_E_HEADER_VERSION_OFF;
 
-            vwr->HEADER_IS_RX       = vVW510024_E_HEADER_IS_RX;
-            vwr->HEADER_IS_TX       = vVW510024_E_HEADER_IS_TX;
-
             vwr->VCID_MASK          = vVW510024_E_VCID_MASK;
             vwr->FLOW_VALID         = vVW510024_E_FLOW_VALID;
             vwr->FCS_ERROR          = v22_E_FCS_ERROR;