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-rw-r--r--src/tuner_fc0012.c50
1 files changed, 22 insertions, 28 deletions
diff --git a/src/tuner_fc0012.c b/src/tuner_fc0012.c
index 4ad2045..768cf1c 100644
--- a/src/tuner_fc0012.c
+++ b/src/tuner_fc0012.c
@@ -206,37 +206,31 @@ int fc0012_set_params(void *dev, uint32_t freq, uint32_t bandwidth)
vco_select = 1;
}
- if (freq >= 45000000) {
- /* From divided value (XDIV) determined the FA and FP value */
- xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
- if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
- xdiv++;
-
- pm = (uint8_t)(xdiv / 8);
- am = (uint8_t)(xdiv - (8 * pm));
-
- if (am < 2) {
- am += 8;
- pm--;
- }
+ /* From divided value (XDIV) determined the FA and FP value */
+ xdiv = (uint16_t)(f_vco / xtal_freq_div_2);
+ if ((f_vco - xdiv * xtal_freq_div_2) >= (xtal_freq_div_2 / 2))
+ xdiv++;
- if (pm > 31) {
- reg[1] = am + (8 * (pm - 31));
- reg[2] = 31;
- } else {
- reg[1] = am;
- reg[2] = pm;
- }
+ pm = (uint8_t)(xdiv / 8);
+ am = (uint8_t)(xdiv - (8 * pm));
- if (reg[1] > 15) {
- fprintf(stderr, "[FC0012] no valid PLL combination "
- "found for %u Hz!\n", freq);
- return -1;
- }
+ if (am < 2) {
+ am += 8;
+ pm--;
+ }
+
+ if (pm > 31) {
+ reg[1] = am + (8 * (pm - 31));
+ reg[2] = 31;
} else {
- /* fix for frequency less than 45 MHz */
- reg[1] = 0x06;
- reg[2] = 0x11;
+ reg[1] = am;
+ reg[2] = pm;
+ }
+
+ if ((reg[1] > 15) || (reg[2] < 0x0b)) {
+ fprintf(stderr, "[FC0012] no valid PLL combination "
+ "found for %u Hz!\n", freq);
+ return -1;
}
/* fix clock out */