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path: root/src/host/trxcon/sched_prim.c
AgeCommit message (Expand)AuthorFilesLines
2019-06-02trxcon/scheduler: fix: do not ignore SACCH prims with odd lengthVadim Yanitskiy1-4/+4
2018-09-28trxcon/scheduler: fix Measurement Reporting on SACCHVadim Yanitskiy1-13/+197
2018-09-28trxcon/sched_prim.c: drop redundant tn validationVadim Yanitskiy1-4/+0
2018-09-28trxcon/scheduler: pass talloc ctx directly to sched_prim_init()Vadim Yanitskiy1-5/+4
2018-09-28trxcon/scheduler: pass lchan state to sched_prim_dequeue()Vadim Yanitskiy1-5/+5
2018-09-16trxcon/scheduler: introduce TCH/H TDMA frame mapping helpresVadim Yanitskiy1-16/+3
2018-08-15trxcon/scheduler: get rid of useless lchan->rsl_modeVadim Yanitskiy1-1/+0
2018-08-15trxcon/scheduler: pass lchan to sched_bad_frame_ind()Vadim Yanitskiy1-6/+2
2018-08-14trxcon/sched_prim.c: properly handle both TCH/H and FACCH/H primsVadim Yanitskiy1-4/+84
2018-08-14trxcon/sched_prim.c: refactor prim dequeuing logicVadim Yanitskiy1-55/+83
2018-04-15trxcon: Prefix SACCH fill frame with L1 headerHarald Welte1-2/+12
2018-03-22trxcon/sched_prim.c: fix: correct the first padding byteVadim Yanitskiy1-8/+9
2018-03-11trxcon/scheduler: transmit dummy frames on CBTX lchansVadim Yanitskiy1-0/+89
2018-01-05trxcon/scheduler: share chan / prim identification helpersVadim Yanitskiy1-9/+0
2018-01-04trxcon/scheduler: FIX: return NULL from TCH dequeue functionVadim Yanitskiy1-6/+6
2017-12-18trxcon/scheduler: prioritize FACCH correctlyVadim Yanitskiy1-35/+43
2017-12-18trxcon/scheduler: move prim management outside lchan handlersVadim Yanitskiy1-7/+51
2017-12-18trxcon/scheduler: separate primitive management codeVadim Yanitskiy1-0/+199
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