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2017-12-18trxcon/scheduler: implement A5/X ciphering supportVadim Yanitskiy3-3/+125
2017-12-18trxcon/scheduler: preprocess UL bursts before sendingVadim Yanitskiy5-12/+27
2017-12-18L1CTL/L1CTL_CRYPTO_REQ: add key length and channel infoVadim Yanitskiy5-11/+19
2017-12-18trxcon/scheduler: prioritize FACCH correctlyVadim Yanitskiy1-35/+43
2017-12-18trxcon/scheduler: move prim management outside lchan handlersVadim Yanitskiy7-79/+118
2017-12-18trxcon/scheduler: separate primitive management codeVadim Yanitskiy7-141/+214
2017-12-18trxcon/scheduler: BUGFIX: distinguish between SACCH and FACCHVadim Yanitskiy1-3/+6
2017-12-16host/trxcon/scheduler: always print error messagesVadim Yanitskiy3-5/+5
2017-12-16host/trxcon/scheduler: inform L2&3 about decoding errorsVadim Yanitskiy4-10/+21
2017-12-16host/trxcon/scheduler: add initial TCH/F channel supportVadim Yanitskiy5-2/+386
2017-12-16host/trxcon/l1ctl.c: handle L1CTL_TRAFFIC_REQVadim Yanitskiy1-0/+40
2017-12-16common/l1ctl.c move TCH bit-ordering to the firmwareVadim Yanitskiy3-40/+54
2017-12-16host/trxcon/scheduler: use GSM_MACBLOCK_LEN definitionVadim Yanitskiy2-5/+8
2017-12-16host/trxcon/scheduler: drop meaningless memset callVadim Yanitskiy1-3/+1
2017-12-16host/trxcon/scheduler: clean up the trx_lchan_stateVadim Yanitskiy3-70/+51
2017-12-16host/trxcon/scheduler: use new libosmocoding API for RACHVadim Yanitskiy1-2/+3
2017-12-09fake_trx: don't sent clock indications until POWERONVadim Yanitskiy2-1/+10
2017-12-09fake_trx/clck_gen.py: reset the clck_src when calling stop()Vadim Yanitskiy1-0/+4
2017-12-09fake_trx/clck_gen.py: send the first indication immediatelyVadim Yanitskiy1-6/+9
2017-12-05host/trxcon: forward Timing Advance value to transceiverVadim Yanitskiy3-1/+32
2017-12-04host/trxcon/trx_if.c: get rid of useless commandsVadim Yanitskiy2-13/+0
2017-12-04host/trxcon/trx_ic.c: use osmo_ubit2sbit() from libosmocoreVadim Yanitskiy1-7/+2
2017-11-23host/trxcon/scheduler: process frames in advanceVadim Yanitskiy4-5/+23
2017-11-21fake_trx: correct brief descriptions of filesVadim Yanitskiy4-7/+7
2017-11-21fake_trx: implement a new tool for burst sendingVadim Yanitskiy2-1/+194
2017-11-21fake_trx/burst_gen.py: remove unused importVadim Yanitskiy1-1/+0
2017-11-21fake_trx/README: correct the branch nameVadim Yanitskiy1-1/+1
2017-11-19fake_trx/ctrl_cmd.py: add help and basic command line optionsVadim Yanitskiy1-8/+53
2017-11-19host/trxcon: fix: use valid names for FSM instancesVadim Yanitskiy2-5/+2
2017-11-19host/trxcon/scheduler: separate logging of data messagesVadim Yanitskiy6-15/+22
2017-11-19host/trxcon/trx_if.c: separate logging of data messagesVadim Yanitskiy3-9/+16
2017-11-19host/trxcon: use LOGP instead of fprintfVadim Yanitskiy2-4/+4
2017-11-19host/trxcon/trx_if.c: fix wrong logging categoryVadim Yanitskiy1-1/+1
2017-11-19host/trxcon/scheduler: fix prim queue flushing functionVadim Yanitskiy1-6/+8
2017-11-19host/trxcon/scheduler: share common declarations of lchan handlersVadim Yanitskiy3-11/+11
2017-11-19host/trxcon/l1ctl.c: handle L1CTL_TCH_MODE_REQVadim Yanitskiy1-0/+36
2017-11-19host/trxcon/l1ctl.c: include DL frame info in L1CTL_DATA_CONFVadim Yanitskiy4-5/+51
2017-11-19host/trxcon/l1ctl.c: use primitive management API for RACHVadim Yanitskiy1-20/+23
2017-11-19host/trxcon/l1ctl.c: share primitive management codeVadim Yanitskiy3-44/+90
2017-11-19host/trxcon/l1ctl.c: don't fill l1ctl_info_ul into a primitiveVadim Yanitskiy2-7/+3
2017-11-19host/trxcon/l1ctl.c: retune TRX only if current ARFCN differsVadim Yanitskiy1-5/+9
2017-11-19host/trxcon/scheduler: send stored tx_power to transceiverVadim Yanitskiy2-2/+2
2017-11-19host/trxcon/l1ctl.c: fix wrong log levelVadim Yanitskiy1-1/+1
2017-11-19host/trxcon: separate logging of L1 Control and L1 DataVadim Yanitskiy4-16/+23
2017-11-19host/trxcon/l1ctl.c: do nothing if CCCH mode matchesVadim Yanitskiy1-2/+14
2017-11-19fake_trx: whitespace fixVadim Yanitskiy2-6/+6
2017-11-19fake_trx: separate DataInterface from burst_gen.pyVadim Yanitskiy2-81/+108
2017-11-19fake_trx: add options to specify fn, tn and pwrVadim Yanitskiy1-5/+31
2017-11-19host/trxcon/scheduler: clean up some includesVadim Yanitskiy3-10/+0
2017-11-19host/trxcon/scheduler: share common code for lchan handlersVadim Yanitskiy3-59/+122
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