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| author | Vadim Yanitskiy <axilirator@gmail.com> | 2017-12-09 01:24:05 +0700 |
|---|---|---|
| committer | Vadim Yanitskiy <axilirator@gmail.com> | 2017-12-09 01:24:05 +0700 |
| commit | 26ecb9460e1871b26a5e3a3c72c2f7163ece2652 (patch) | |
| tree | c47b86913d020b30c1522eea83fd091c63859007 | |
| parent | 05ff6b06674dd3b9c310e3b27e5bad821cd6d41c (diff) | |
fake_trx/clck_gen.py: reset the clck_src when calling stop()
Change-Id: I1043f71a2cbe856a0cb605db8a7feab9defa6afd
| -rwxr-xr-x | src/target/fake_trx/clck_gen.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/target/fake_trx/clck_gen.py b/src/target/fake_trx/clck_gen.py index 1eb970a5..088155b7 100755 --- a/src/target/fake_trx/clck_gen.py +++ b/src/target/fake_trx/clck_gen.py @@ -51,6 +51,7 @@ class CLCKGen: def __init__(self, clck_links, clck_start = 0, ind_period = 102): self.clck_links = clck_links self.ind_period = ind_period + self.clck_start = clck_start self.clck_src = clck_start # Calculate counter time @@ -68,6 +69,9 @@ class CLCKGen: self.timer.cancel() self.timer = None + # Reset the clock source + self.clck_src = self.clck_start + def send_clck_ind(self): # Keep clock cycle if self.clck_src % self.GSM_SUPERFRAME >= 0: |