diff options
| author | Mychaela Falconia <falcon@freecalypso.org> | 2020-09-28 19:31:30 +0000 |
|---|---|---|
| committer | Harald Welte <laforge@osmocom.org> | 2020-10-01 01:48:43 +0200 |
| commit | 7b2820526ab9ceafa9027f1b3a81f86c91837a2d (patch) | |
| tree | d2dfde94473698086ba6b3fdeb0b597f908869c2 /src/target/firmware | |
| parent | e8bad6eaa6f4e9036740d02a38112f6837524c78 (diff) | |
firmware: gtm900b: fix MEMIF configuration
* Switch Calypso output CS4/ADD22 to ADD22 function as needed
in order to access the upper half of the flash on GTM900 hw
variant MG01GSMT.
* Set WS=4 for safety - please refer to this technical article for
the underlying theory:
https://www.freecalypso.org/hg/freecalypso-docs/file/tip/MEMIF-wait-states
Related: OS#4769
Change-Id: I1923243937d7251f6bcfe71a0b1cc0e206a81cfa
Diffstat (limited to 'src/target/firmware')
| -rw-r--r-- | src/target/firmware/board/gtm900b/init.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/target/firmware/board/gtm900b/init.c b/src/target/firmware/board/gtm900b/init.c index f04d3140..8de99563 100644 --- a/src/target/firmware/board/gtm900b/init.c +++ b/src/target/firmware/board/gtm900b/init.c @@ -50,6 +50,7 @@ #define ARMIO_LATCH_OUT 0xfffe4802 #define IO_CNTL_REG 0xfffe4804 +#define ARM_CONF_REG 0xfffef006 #define ASIC_CONF_REG 0xfffef008 #define IO_CONF_REG 0xfffef00a #define LPG_LCR_REG 0xfffe7800 @@ -77,13 +78,28 @@ static void board_io_init(void) /* Set LPG output permanently on (power LED) */ writew(1, LPG_PM_REG); writew((1 << 7), LPG_LCR_REG); + + /* configure ADD(22), needed for second half of flash on MG01GSMT */ + reg = readw(ARM_CONF_REG); + reg |= (1 << 3); + writew(reg, ARM_CONF_REG); } void board_init(int with_irq) { - /* Configure the memory interface */ - calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); - calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); + /* + * Configure the memory interface. + * Huawei's official fw sets WS=4 for RAM, but not for flash - + * but let's be consistent and use WS=4 for both. Please refer + * to this technical article for the underlying theory: +https://www.freecalypso.org/hg/freecalypso-docs/file/tip/MEMIF-wait-states + */ + calypso_mem_cfg(CALYPSO_nCS0, 4, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS1, 4, CALYPSO_MEM_16bit, 1); + /* + * The remaining 3 chip selects are unused on this hw, + * thus their settings are dummies. + */ calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1); calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1); |