diff options
| author | Philipp Maier <pmaier@sysmocom.de> | 2018-09-19 13:40:21 +0200 |
|---|---|---|
| committer | Neels Hofmeyr <nhofmeyr@sysmocom.de> | 2018-09-19 14:01:10 +0000 |
| commit | 5f2eb150742bd793f2f61fb5cfe2b2df707c0093 (patch) | |
| tree | 08122f798a25f03a2ca29ba001cc25b1534f9bf5 /tests/gsm0808/gsm0808_test.ok | |
| parent | 28fc078f9cc02b6c731b0d2e5813857d2ec03ea1 (diff) | |
gsm0808: add function to convert amr gsm0408 setings to gsm0808
Add a function to convert struct gsm48_multi_rate_conf, which holds the
codec settings for AMR, to S0-S15 bit representation as defined in
3GPP TS 48.008 3.2.2.49
This resurrects change-id I4e656731b16621736c7a2f4e64d9ce63b1064e98
which was reverted in I9e0d405e303ed86d23703ca6362e958dddb2f861
due to gsm0808_test failing.
The test failure is fixed by properly clearing the struct
gsm48_multirate_cfg prior to running tests (add memset(0)).
Change-Id: Ia782e21c206c15e840226d79b4209d13658ee916
Related: OS#3548
Diffstat (limited to 'tests/gsm0808/gsm0808_test.ok')
| -rw-r--r-- | tests/gsm0808/gsm0808_test.ok | 225 |
1 files changed, 225 insertions, 0 deletions
diff --git a/tests/gsm0808/gsm0808_test.ok b/tests/gsm0808/gsm0808_test.ok index 6cd7982b..dc1debac 100644 --- a/tests/gsm0808/gsm0808_test.ok +++ b/tests/gsm0808/gsm0808_test.ok @@ -74,4 +74,229 @@ test_gsm0808_enc_dec_cell_id_lai_and_lac: encoded: 05 06 04 21 63 54 23 42 (rc = test_gsm0808_enc_dec_cell_id_ci: encoded: 05 03 02 04 23 (rc = 5) test_gsm0808_enc_dec_cell_id_lac_and_ci: encoded: 05 05 01 04 23 02 35 (rc = 7) test_gsm0808_enc_dec_cell_id_global: encoded: 05 08 00 21 63 54 23 42 04 23 (rc = 10) +Testing gsm0808_sc_cfg_from_gsm48_mr_cfg(): +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 0000 = 0b0000000000000000 +Result (hr): + S15-S0 = 0000 = 0b0000000000000000 + +Input: + m4_75= 1 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 5703 = 0b0101011100000011 +Result (hr): + S15-S0 = 0703 = 0b0000011100000011 + +Input: + m4_75= 0 smod= 0 + m5_15= 1 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 0000 = 0b0000000000000000 +Result (hr): + S15-S0 = 0000 = 0b0000000000000000 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 1 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 5706 = 0b0101011100000110 +Result (hr): + S15-S0 = 0706 = 0b0000011100000110 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 1 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 1608 = 0b0001011000001000 +Result (hr): + S15-S0 = 0608 = 0b0000011000001000 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 1 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 0412 = 0b0000010000010010 +Result (hr): + S15-S0 = 0412 = 0b0000010000010010 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 1 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 4020 = 0b0100000000100000 +Result (hr): + S15-S0 = 0020 = 0b0000000000100000 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 1 + m12_2= 0 +Result (fr): + S15-S0 = 1040 = 0b0001000001000000 +Result (hr): + S15-S0 = 0000 = 0b0000000000000000 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 1 +Result (fr): + S15-S0 = 4082 = 0b0100000010000010 +Result (hr): + S15-S0 = 0002 = 0b0000000000000010 + +Input: + m4_75= 1 smod= 0 + m5_15= 1 spare= 0 + m5_90= 1 icmi= 0 + m6_70= 1 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 570f = 0b0101011100001111 +Result (hr): + S15-S0 = 070f = 0b0000011100001111 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 1 ver= 0 + m7_95= 1 + m10_2= 1 + m12_2= 1 +Result (fr): + S15-S0 = 54f2 = 0b0101010011110010 +Result (hr): + S15-S0 = 0432 = 0b0000010000110010 + +Input: + m4_75= 0 smod= 0 + m5_15= 0 spare= 0 + m5_90= 1 icmi= 0 + m6_70= 1 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 0 + m10_2= 1 + m12_2= 1 +Result (fr): + S15-S0 = 57ce = 0b0101011111001110 +Result (hr): + S15-S0 = 070e = 0b0000011100001110 + +Input: + m4_75= 1 smod= 0 + m5_15= 1 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 1 ver= 0 + m7_95= 1 + m10_2= 0 + m12_2= 0 +Result (fr): + S15-S0 = 5733 = 0b0101011100110011 +Result (hr): + S15-S0 = 0733 = 0b0000011100110011 + +Input: + m4_75= 0 smod= 0 + m5_15= 1 spare= 0 + m5_90= 0 icmi= 0 + m6_70= 1 nscb= 0 + m7_40= 0 ver= 0 + m7_95= 1 + m10_2= 0 + m12_2= 1 +Result (fr): + S15-S0 = 56aa = 0b0101011010101010 +Result (hr): + S15-S0 = 062a = 0b0000011000101010 + +Input: + m4_75= 1 smod= 0 + m5_15= 0 spare= 0 + m5_90= 1 icmi= 0 + m6_70= 0 nscb= 0 + m7_40= 1 ver= 0 + m7_95= 0 + m10_2= 1 + m12_2= 0 +Result (fr): + S15-S0 = 5757 = 0b0101011101010111 +Result (hr): + S15-S0 = 0717 = 0b0000011100010111 + +Input: + m4_75= 1 smod= 0 + m5_15= 1 spare= 0 + m5_90= 1 icmi= 0 + m6_70= 1 nscb= 0 + m7_40= 1 ver= 0 + m7_95= 1 + m10_2= 1 + m12_2= 1 +Result (fr): + S15-S0 = 57ff = 0b0101011111111111 +Result (hr): + S15-S0 = 073f = 0b0000011100111111 + Done |