RF: MT6140 initial supportHEADmaster

This patch provides initial drivers for BPI, BSI, BFE and MT6140.
Currently it just supports TX path on low band (for testing purposes).

Signed-off-by: xpumami <xpumami@xpumami-OptiPlex-760.(none)>

7 files changed, 341 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-mtk/bfe.h b/arch/arm/include/asm/arch-mtk/bfe.h
new file mode 100644
index 000000000..58e8b974f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mtk/bfe.h
@@ -0,0 +1,56 @@
+#ifndef _MTK_BFE_H
+#define _MTK_BFE_H
+
+/* MTK Baseband Front End */
+
+/* Chapter 10 of MT6235 Data Sheet */
+#define	BFE_CON			(MTK_BFE_BASE + 0x0000)
+#define	BFE_STA			(MTK_BFE_BASE + 0x0004)
+
+/* RX path */
+#define	BFE_RX_CFG		(MTK_BFE_BASE + 0x0010)
+#define	BFE_RX_CON		(MTK_BFE_BASE + 0x0014)
+#define	BFE_RX_PM_CON		(MTK_BFE_BASE + 0x0018)
+#define	BFE_RX_FIR_CSID_CON	(MTK_BFE_BASE + 0x001C)
+#define	BFE_RX_RAM0_CS0		(MTK_BFE_BASE + 0x0070)
+#define	BFE_RX_RAM1_CS0		(MTK_BFE_BASE + 0x0020)
+#define	BFE_RX_HPWR_STS		(MTK_BFE_BASE + 0x00B0)
+#define	BFE_RX_BPWR_STS		(MTK_BFE_BASE + 0x00B4)
+
+#define BFE_RX_RAM0_CS(n)	(BFE_RX_RAM0_CS0 + 4 * n)
+#define BFE_RX_RAM1_CS(n)	(BFE_RX_RAM0_CS1 + 4 * n)
+
+/* TX path */
+#define	BFE_TX_CFG		(MTK_BFE_BASE + 0x0060)
+#define	BFE_TX_CON		(MTK_BFE_BASE + 0x0064)
+#define	BFE_TX_OFF		(MTK_BFE_BASE + 0x0068)
+
+/* BFE_TX_CFG register fields */
+#define BFE_TX_CFG_APNDEN	(1 << 0)
+#define BFE_TX_CFG_RPSEL_RAMP1	(0 << 1)
+#define BFE_TX_CFG_RPSEL_RAMP2	(1 << 1)
+#define BFE_TX_CFG_RPSEL_RAMP3	(3 << 1)
+#define BFE_TX_CFG_INTEN	(1 << 3)
+#define BFE_TX_CFG_MDBYP	(1 << 4)
+#define BFE_TX_CFG_SGEN		(1 << 5)
+#define BFE_TX_CFG_NORMAL	(0 << 6)
+#define BFE_TX_CFG_ALL0GEN	(1 << 6)
+#define BFE_TX_CFG_ALL1GEN	(2 << 6)
+#define BFE_TX_CFG_SW_QBCNT_SHIFT	8
+#define BFE_TX_CFG_GMSK_1TAP	(0 << 13)
+#define BFE_TX_CFG_GMSK_0TAP	(1 << 13)
+#define BFE_TX_CFG_GMSK_2TAP	(2 << 13)
+
+/* BFE_TX_CON register fields */
+#define BFE_TX_CON_IQSWP	(1 << 0)
+#define BFE_TX_CON_MDSEL1	(1 << 2)
+#define BFE_TX_CON_MDSEL2	(1 << 3)
+#define BFE_TX_CON_MDSEL3	(1 << 4)
+#define BFE_TX_CON_MDSEL4	(1 << 5)
+#define BFE_TX_CON_PHSEL_SHIFT	8
+#define BFE_TX_CON_GMSK_0QB	(0 << 12)
+#define BFE_TX_CON_GMSK_1QB	(1 << 12)
+#define BFE_TX_CON_GMSK_2QB	(2 << 12)
+#define BFE_TX_CON_GMSK_3QB	(3 << 12)
+
+#endif /* _MTK_BFE_H */
diff --git a/arch/arm/include/asm/arch-mtk/bpi.h b/arch/arm/include/asm/arch-mtk/bpi.h
new file mode 100644
index 000000000..70159a77f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mtk/bpi.h
@@ -0,0 +1,24 @@
+#ifndef _MTK_BPI_H
+#define _MTK_BPI_H
+
+/* MTK Baseband Parallel Interface */
+
+/* Chapter 9.2 of MT6235 Data Sheet */
+#define	BPI_CON		(MTK_BPI_BASE + 0x0000)
+#define BPI_BUF0	(MTK_BPI_BASE + 0x0004)
+#define BPI_BUFI	(MTK_BPI_BASE + 0x00ac)
+#define	BPI_ENA0	(MTK_BPI_BASE + 0x00b0)
+#define BPI_ENA1	(MTK_BPI_BASE + 0x00b4)
+#define BPI_ENA2	(MTK_BPI_BASE + 0x00b8)
+
+#define BPI_BUF(n)	(BPI_BUF0 + ((n) * 4))
+
+#define MTK_BPI(n)	(n)
+
+/* BPI_CON bit fields */
+#define BPI_CON_PETEV	1
+#define BPI_CON_PINM0	2
+#define BPI_CON_PINM1	3
+#define BPI_CON_PINM2	4
+
+#endif /* _MTK_BPI_H */
diff --git a/arch/arm/include/asm/arch-mtk/bsi.h b/arch/arm/include/asm/arch-mtk/bsi.h
new file mode 100644
index 000000000..c6524fef6
--- /dev/null
+++ b/arch/arm/include/asm/arch-mtk/bsi.h
@@ -0,0 +1,50 @@
+#ifndef _MTK_BSI_H
+#define _MTK_BSI_H
+
+/* MTK Baseband Serial Interface */
+
+#define	BSI_CON		(MTK_BSI_BASE + 0x0000)
+#define	BSI_D0_CON	(MTK_BSI_BASE + 0x0004)
+#define	BSI_D0_DAT	(MTK_BSI_BASE + 0x0008)
+#define	BSI_D40_CON	(MTK_BSI_BASE + 0x0144)
+#define	BSI_D40_DAT2	(MTK_BSI_BASE + 0x0148)
+#define	BSI_D40_DAT1	(MTK_BSI_BASE + 0x014C)
+#define	BSI_D40_DAT0	(MTK_BSI_BASE + 0x0150)
+#define BSI_ENA_0	(MTK_BSI_BASE + 0x0190)
+#define	BSI_ENA_1	(MTK_BSI_BASE + 0x0194)
+#define	BSI_IO_CON	(MTK_BSI_BASE + 0x0198)
+#define BSI_DOUT	(MTK_BSI_BASE + 0x019c)
+#define	BSI_DIN		(MTK_BSI_BASE + 0x01a0)
+#define	BSI_PAIR_NUM	(MTK_BSI_BASE + 0x01a4)
+
+/* Compute offset of BSI_D0_CON / BSI_D0_DAT registers */
+#define BSI_Dn_32BIT_CON(x)	(BSI_D0_CON + (x * 8))
+#define BSI_Dn_32BIT_DAT(x)	(BSI_D0_DAT + (x * 8))
+#define BSI_Dn_78BIT_CON(x)	(BSI_D40_CON + (x * 16))
+#define BSI_Dn_78BIT_DAT0(x)	(BSI_D40_DAT0 + (x * 16))
+#define BSI_Dn_78BIT_DAT1(x)	(BSI_D40_DAT1 + (x * 16))
+#define BSI_Dn_78BIT_DAT2(x)	(BSI_D40_DAT2 + (x * 16))
+
+/* MT6235 Section 9.1.1 */
+#define BSI_CON_CLK_POL_INV	(1 << 0)
+#define BSI_CON_CLK_SPD_52_2	(0 << 1)	/* 26 MHz */
+#define BSI_CON_CLK_SPD_52_4	(1 << 1)	/* 13 MHz */
+#define BSI_CON_CLK_SPD_52_6	(2 << 1)	/* 8.67 MHz */
+#define BSI_CON_CLK_SPD_52_8	(3 << 1)	/* 6.50 MHz */
+#define BSI_CON_IMOD		(1 << 3)
+#define BSI_CON_EN0_LEN_SHORT	(1 << 4)
+#define BSI_CON_EN0_POL_INV	(1 << 5)
+#define BSI_CON_EN1_LEN_SHORT	(1 << 6)
+#define BSI_CON_EN1_POL_INV	(1 << 7)
+#define BSI_CON_SETENV		(1 << 8)
+
+/* how the length is encoded in BSI_Dn_CON */
+#define BSI_Dn_LEN(n)		(((n-1) & 0x7f) << 8)
+#define BSI_Dn_ISB		0x8000		/* select device 1 */
+
+/* Immediate download EVENT ID */
+#define BSI_EVENT_ID_IMMEDIATE	0x1F
+
+#define BSI_EVENT_ID(n)		(n)
+
+#endif /* _MTK_BSI_H */
diff --git a/arch/arm/include/asm/arch-mtk/gpio.h b/arch/arm/include/asm/arch-mtk/gpio.h
index bba301d77..d5c06ec30 100644
--- a/arch/arm/include/asm/arch-mtk/gpio.h
+++ b/arch/arm/include/asm/arch-mtk/gpio.h
@@ -82,6 +82,47 @@
 #define MTK_GPIO_CLK_OUT9	(MTK_GPIO_BASE + 0x3800)
 #define MTK_GPIO_CLK_OUT10	(MTK_GPIO_BASE + 0x3900)
 
+/* MTK_GPIO_MODE_3 bit field definitions. */
+#define MTK_GPIO_MODE3_GPIO16		0
+#define MTK_GPIO_MODE3_GPIO16_ALT1	1
+#define MTK_GPIO_MODE3_GPIO16_ALT2	2
+#define MTK_GPIO_MODE3_GPIO16_ALT3	3
+
+#define MTK_GPIO_MODE3_GPIO17		(0 << 2)
+#define MTK_GPIO_MODE3_GPIO17_ALT1	(1 << 2)
+#define MTK_GPIO_MODE3_GPIO17_ALT2	(2 << 2)
+#define MTK_GPIO_MODE3_GPIO17_ALT3	(3 << 2)
+
+#define MTK_GPIO_MODE3_GPIO18		(0 << 4)
+#define MTK_GPIO_MODE3_GPIO18_ALT1	(1 << 4)
+#define MTK_GPIO_MODE3_GPIO18_ALT2	(2 << 4)
+#define MTK_GPIO_MODE3_GPIO18_ALT3	(3 << 4)
+
+#define MTK_GPIO_MODE3_GPIO19		(0 << 6)
+#define MTK_GPIO_MODE3_GPIO19_ALT1	(1 << 6)
+#define MTK_GPIO_MODE3_GPIO19_ALT2	(2 << 6)
+#define MTK_GPIO_MODE3_GPIO19_ALT3	(3 << 6)
+
+#define MTK_GPIO_MODE3_GPIO20		(0 << 8)
+#define MTK_GPIO_MODE3_GPIO20_ALT1	(1 << 8)
+#define MTK_GPIO_MODE3_GPIO20_ALT2	(2 << 8)
+#define MTK_GPIO_MODE3_GPIO20_ALT3	(3 << 8)
+
+#define MTK_GPIO_MODE3_GPIO21		(0 << 10)
+#define MTK_GPIO_MODE3_GPIO21_ALT1	(1 << 10)
+#define MTK_GPIO_MODE3_GPIO21_ALT2	(2 << 10)
+#define MTK_GPIO_MODE3_GPIO21_ALT3	(3 << 10)
+
+#define MTK_GPIO_MODE3_GPIO22		(0 << 12)
+#define MTK_GPIO_MODE3_GPIO22_ALT1	(1 << 12)
+#define MTK_GPIO_MODE3_GPIO22_ALT2	(2 << 12)
+#define MTK_GPIO_MODE3_GPIO22_ALT3	(3 << 12)
+
+#define MTK_GPIO_MODE3_GPIO23		(0 << 14)
+#define MTK_GPIO_MODE3_GPIO23_ALT1	(1 << 14)
+#define MTK_GPIO_MODE3_GPIO23_ALT2	(2 << 14)
+#define MTK_GPIO_MODE3_GPIO23_ALT3	(3 << 14)
+
 /* MTK_GPIO_MODE_4 bit field definitions. */
 #define MTK_GPIO_MODE4_GPIO24		0
 #define MTK_GPIO_MODE4_GPIO24_ALT1	1
diff --git a/arch/arm/include/asm/arch-mtk/mt6140.h b/arch/arm/include/asm/arch-mtk/mt6140.h
new file mode 100644
index 000000000..4d70dbe6f
--- /dev/null
+++ b/arch/arm/include/asm/arch-mtk/mt6140.h
@@ -0,0 +1,70 @@
+#ifndef _MTK_MT6140_H
+#define _MTK_MT6140_H
+
+enum mt6140_band {
+	MTRF_BAND_GSM850	= 0,
+	MTRF_BAND_GSM900	= 1,
+	MTRF_BAND_GSM1800	= 2,
+	MTRF_BAND_GSM1900	= 3,
+};
+
+#define MT6140_CW0_SYNCP_SHIFT		0
+#define MT6140_CW0_SYNPW		(1 << 2)
+#define MT6140_CW0_DIEN			(1 << 3)
+#define MT6140_CW0_FLT			(1 << 4)
+#define MT6140_CW0_AFC_SHIFT		5
+#define MT6140_CW0_VCO_SEL		(1 << 11)
+#define MT6140_CW0_GPO			(1 << 12)
+/* This field is shifted by 1-bit comparing to MT6139 */
+#define MT6140_CW0_POR			(1 << 14)
+
+#define MT6140_CW1_NFRACT_SHIFT		0
+#define MT6140_CW1_NINT_SHIFT		8
+#define MT6140_CW1_BAND_SHIFT		16
+#define MT6140_CW1_BUF_MODE		(1 << 15)
+#define MT6140_CW1_TRX			(1 << 18)
+
+#define MT6140_CW2_GAINTBL_SHIFT	0
+#define MT6140_CW2_MODE_SHIFT		6
+#define MT6140_CW2_AUTO_CAL		(1 << 9)
+#define MT6140_CW2_DCD_AQ_SHIFT		10
+#define MT6140_CW2_DCD_AI_SHIFT		16
+
+#define MT6140_CW9_DCD_CQ_SHIFT		0
+#define MT6140_CW9_DCD_BQ_SHIFT		7
+#define MT6140_CW9_PWR_DAC_C		(1 << 14)
+#define MT6140_CW9_PWR_DAC_B		(1 << 15)
+#define MT6140_CW9_PWR_DAC_A		(1 << 16)
+#define MT6140_CW9_AM_ENABLE		(1 << 17)
+
+enum mt6140_cw2_mode {
+	MODE_SLEEP	= 0x0,
+	MODE_WARM_UP	= 0x1,
+	MODE_RECEIVE	= 0x3,
+	MODE_TRANSMIT	= 0x4,
+};
+
+#define MT6140_CW11_TX_CTL		(1 << 0)
+#define MT6140_CW11_TXG_IQM		(1 << 1)
+#define MT6140_CW11_TXD_IQM		(1 << 2)
+#define MT6140_CW11_TX_DIV2		(1 << 3)
+#define MT6140_CW11_TX_DIV4		(1 << 4)
+#define MT6140_CW11_TXG_BUF		(1 << 5)
+#define MT6140_CW11_TXD_BUF		(1 << 6)
+#define MT6140_CW11_TXMODGAIN_SHIFT	7
+#define MT6140_CW11_TXFLT_SHIFT	10
+#define MT6140_CW11_TXAPC_SHIFT		14
+#define MT6140_CW11_TXPW_SHIFT		16
+#define MT6140_CW11_TXBIAST_SHIFT	18
+#define MT6140_CW11_TXDIV_GC0		(1 << 20)
+#define MT6140_CW11_TXDIV_GC1		(1 << 21)
+
+#define BPI_HB_TX			(1 << 0)
+#define BPI_PCS_RX			(1 << 1)
+#define BPI_LB_TX			(1 << 2)
+#define BPI_PAEN			(1 << 4)
+#define BPI_BANDSW			(1 << 5)
+#define BPI_MODE_PA			(1 << 7)
+#define BPI_RFVCOEN			(1 << 9)
+
+#endif /* _MTK_MT6140_H */
diff --git a/arch/arm/include/asm/arch-mtk/system.h b/arch/arm/include/asm/arch-mtk/system.h
index 9ceb90576..082b3ee7e 100644
--- a/arch/arm/include/asm/arch-mtk/system.h
+++ b/arch/arm/include/asm/arch-mtk/system.h
@@ -47,6 +47,9 @@
 #define MTK_CONFG_PDN_CLR1	(MTK_CONFG_BASE + 0x324)
 #define MTK_CONFG_PDN_CLR2	(MTK_CONFG_BASE + 0x328)
 #define MTK_CONFG_PDN_CLR3	(MTK_CONFG_BASE + 0x32C)
+#define MTK_CONFG_PDN_CON4	(MTK_CONFG_BASE + 0x330)
+#define MTK_CONFG_PDN_SET4	(MTK_CONFG_BASE + 0x334)
+#define MTK_CONFG_PDN_CLR4	(MTK_CONFG_BASE + 0x338)
 
 /* CONFG_MCUCLK_CON bit fields definitions */
 #define MCUCLK_CON_AHBX8CLK_SHIFT	(0)
@@ -90,6 +93,16 @@
 #define PDN_CON2_BPI		(1 << 3)
 #define PDN_CON2_AFC		(1 << 4)
 #define PDN_CON2_APC		(1 << 5)
+#define PDN_CON2_FCS		(1 << 6)
+#define PDN_CON2_AUXAD		(1 << 7)
+#define PDN_CON2_VAFE		(1 << 8)
+#define PDN_CON2_BFE		(1 << 9)
+#define PDN_CON2_GCC		(1 << 10)
+#define PDN_CON2_DIV		(1 << 11)
+#define PDN_CON2_AAFE		(1 << 12)
+#define PDN_CON2_I2C		(1 << 13)
+#define PDN_CON2_BBRX		(1 << 14)
+#define PDN_CON2_GMSK		(1 << 14)
 
 /*
  * Reset Generation Unit block section
diff --git a/arch/arm/include/asm/arch-mtk/tdma_timer.h b/arch/arm/include/asm/arch-mtk/tdma_timer.h
new file mode 100644
index 000000000..abaecb128
--- /dev/null
+++ b/arch/arm/include/asm/arch-mtk/tdma_timer.h
@@ -0,0 +1,87 @@
+#ifndef _MTK_TDMA_H
+#define _MTK_TDMA_H
+
+/* MTK TDMA Timer */
+
+/* MT6235 Section 11 */
+
+/* Read current quarter bit count */
+#define TDMA_TQCNT		(MTK_TDMA_BASE + 0x0000)
+/* Latched Qbit counter reset position */
+#define	TDMA_WRAP		(MTK_TDMA_BASE + 0x0004)
+/* Direct Qbit counter reset position */
+#define TDMA_WRAPIMD		(MTK_TDMA_BASE +  0x0008)
+/* Event latch position */
+#define TDMA_EVTVAL		(MTK_TDMA_BASE + 0x000c)
+/* DSP software control */
+#define TDMA_DTIRQ		(MTK_TDMA_BASE +  0x0010)
+/* MCU software control */
+#define DMA_CTIRQ1		(MTK_TDMA_BASE + 0x0014)
+#define TDMA_CTIRQ2		(MTK_TDMA_BASE + 0x0018)
+/* AFC control */
+#define TDMA_AFC0		(MTK_TDMA_BASE + 0x0020)
+#define TDMA_AFC1		(MTK_TDMA_BASE + 0x0024)
+#define TDMA_AFC2		(MTK_TDMA_BASE + 0x0028)
+#define TDMA_AFC3		(MTK_TDMA_BASE + 0x002c)
+
+/* Downlink control */
+#define TDMA_BDLON0		(MTK_TDMA_BASE + 0x0030)
+#define TDMA_BDLOFF0		(MTK_TDMA_BASE + 0x0034)
+#define TDMA_BDLON1		(MTK_TDMA_BASE + 0x0038)
+#define TDMA_BDLOFF1		(MTK_TDMA_BASE + 0x003C)
+#define TDMA_BDLON2		(MTK_TDMA_BASE + 0x0040)
+#define TDMA_BDLOFF2		(MTK_TDMA_BASE + 0x0044)
+#define TDMA_BDLON3		(MTK_TDMA_BASE + 0x0048)
+#define TDMA_BDLOFF3		(MTK_TDMA_BASE + 0x004C)
+#define TDMA_BDLON4		(MTK_TDMA_BASE + 0x0050)
+#define TDMA_BDLOFF4		(MTK_TDMA_BASE + 0x0054)
+#define TDMA_BDLON5		(MTK_TDMA_BASE + 0x0058)
+#define TDMA_BDLOFF5		(MTK_TDMA_BASE + 0x005C)
+
+/* Uplink control */
+#define TDMA_BULON0		(MTK_TDMA_BASE + 0x0060)
+#define TDMA_BULOFF0		(MTK_TDMA_BASE + 0x0064)
+#define TDMA_BULON1		(MTK_TDMA_BASE + 0x0068)
+#define TDMA_BULOFF1		(MTK_TDMA_BASE + 0x006C)
+#define TDMA_BULON2		(MTK_TDMA_BASE + 0x0070)
+#define TDMA_BULOFF2		(MTK_TDMA_BASE + 0x0074)
+#define TDMA_BULON3		(MTK_TDMA_BASE + 0x0078)
+#define TDMA_BULOFF3		(MTK_TDMA_BASE + 0x007C)
+
+/* APC control */
+#define TDMA_APC0		(MTK_TDMA_BASE + 0x0090)
+/* BSI event */
+#define TDMA_BSI0		(MTK_TDMA_BASE + 0x00b0)
+/* BPI event */
+#define TDMA_BPI0		(MTK_TDMA_BASE + 0x0100)
+/* Auxiliary ADC event */
+#define TDMA_AUXEV0		(MTK_TDMA_BASE + 0x0400)
+#define TDMA_AUXEV1		(MTK_TDMA_BASE + 0x0404)
+/* Event Control */
+#define TDMA_EVTENA0		(MTK_TDMA_BASE + 0x0150)
+#define TDMA_EVTENA1		(MTK_TDMA_BASE + 0x0154)
+#define TDMA_EVTENA2		(MTK_TDMA_BASE + 0x0158)
+#define TDMA_EVTENA3		(MTK_TDMA_BASE + 0x015c)
+#define TDMA_EVTENA4		(MTK_TDMA_BASE + 0x0160)
+#define TDMA_EVTENA5		(MTK_TDMA_BASE + 0x0164)
+#define TDMA_EVTENA6		(MTK_TDMA_BASE + 0x0168)
+#define TDMA_EVTENA7		(MTK_TDMA_BASE + 0x016c)
+#define TDMA_WRAPOFS		(MTK_TDMA_BASE + 0x0170)
+#define TDMA_REGBIAS		(MTK_TDMA_BASE + 0x0174)
+#define TDMA_DTXCON		(MTK_TDMA_BASE + 0x0180)
+#define TDMA_RXCON		(MTK_TDMA_BASE + 0x0184)
+#define TDMA_BDLCON		(MTK_TDMA_BASE + 0x0188)
+#define TDMA_BULCON1		(MTK_TDMA_BASE + 0x018c)
+#define TDMA_BULCON2		(MTK_TDMA_BASE + 0x0190)
+#define TDMA_FB_FLAG		(MTK_TDMA_BASE + 0x0194)
+#define TDMA_FB_CLRI		(MTK_TDMA_BASE + 0x0198)
+
+#define TDMA_BSI(n)		(TDMA_BSI0 + (n)*4)
+#define TDMA_BPI(n)		(TDMA_BPI0 + (n)*4)
+#define TDMA_APC(n)		(TDMA_APC0 + (n)*4)
+#define TDMA_BULON(n)		(TDMA_BULON0 + (n)*8)
+#define TDMA_BULOFF(n)		(TDMA_BULOFF0 + (n)*8)
+#define TDMA_BDLON(n)		(TDMA_BDLON0 + (n)*8)
+#define TDMA_BDLOFF(n)		(TDMA_BDLOFF0 + (n)*8)
+
+#endif /* _MTK_TDMA_H */