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authorHarald Welte <laforge@osmocom.org>2020-12-29 17:30:02 +0100
committerHarald Welte <laforge@osmocom.org>2020-12-29 17:30:02 +0100
commitb161f50e72ac5e2078f62c9830f7b687206501b3 (patch)
treec785d980869476383acaa4e4759c872d17f4bd23
parent6dc3393177ea215632faff8534e98755083f8c53 (diff)
add full-size smartcard to FPC adapter design files
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GBL805
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GBO602
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GBP247
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GBS294
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GML247
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GTL1754
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GTO2253
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GTP307
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.GTS337
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.TXT52
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.dri36
-rw-r--r--hardware/smartcard-fpc/gerber/smartcard-fpc.gpi49
-rw-r--r--hardware/smartcard-fpc/smartcard-fpc.brd722
-rw-r--r--hardware/smartcard-fpc/smartcard-fpc.sch929
14 files changed, 8634 insertions, 0 deletions
diff --git a/hardware/smartcard-fpc/gerber/smartcard-fpc.GBL b/hardware/smartcard-fpc/gerber/smartcard-fpc.GBL
new file mode 100644
index 0000000..003dbc2
--- /dev/null
+++ b/hardware/smartcard-fpc/gerber/smartcard-fpc.GBL
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new file mode 100644
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--- /dev/null
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new file mode 100644
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new file mode 100644
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--- /dev/null
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new file mode 100644
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new file mode 100644
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new file mode 100644
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diff --git a/hardware/smartcard-fpc/gerber/smartcard-fpc.dri b/hardware/smartcard-fpc/gerber/smartcard-fpc.dri
new file mode 100644
index 0000000..b4008dc
--- /dev/null
+++ b/hardware/smartcard-fpc/gerber/smartcard-fpc.dri
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+Generated by EAGLE CAM Processor 7.7.0
+
+Drill Station Info File: /space/home/laforge/simcard-fpc.dri
+
+ Date : 12/29/20 5:17 PM
+ Drills : generated
+ Device : Excellon drill station, coordinate format 2.5 inch
+
+Parameter settings:
+
+ Tolerance Drill + : 0.00 %
+ Tolerance Drill - : 0.00 %
+ Rotate : no
+ Mirror : no
+ Optimize : yes
+ Auto fit : yes
+ OffsetX : 0inch
+ OffsetY : 0inch
+ Layers : Drills Holes
+
+Drill File Info:
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+ Data Mode : Absolute
+ Units : 1/100000 Inch
+
+Drills used:
+
+ Code Size used
+
+ T01 0.0118inch 45
+
+Total number of drills: 45
+
+Plotfiles:
+
+ /space/home/laforge/simcard-fpc.TXT
diff --git a/hardware/smartcard-fpc/gerber/smartcard-fpc.gpi b/hardware/smartcard-fpc/gerber/smartcard-fpc.gpi
new file mode 100644
index 0000000..fbad882
--- /dev/null
+++ b/hardware/smartcard-fpc/gerber/smartcard-fpc.gpi
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+Generated by EAGLE CAM Processor 7.7.0
+
+Photoplotter Info File: /space/home/laforge/simcard-fpc.gpi
+
+ Date : 12/29/20 5:17 PM
+ Plotfile : /space/home/laforge/simcard-fpc.GTL
+ Apertures : generated:
+ Device : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
+
+Parameter settings:
+
+ Emulate Apertures : no
+ Tolerance Draw + : 0.00 %
+ Tolerance Draw - : 0.00 %
+ Tolerance Flash + : 0.00 %
+ Tolerance Flash - : 0.00 %
+ Rotate : no
+ Mirror : no
+ Optimize : yes
+ Auto fit : yes
+ OffsetX : 0inch
+ OffsetY : 0inch
+
+Plotfile Info:
+
+ Coordinate Format : 2.5
+ Coordinate Units : Inch
+ Data Mode : Absolute
+ Zero Suppression : None
+ End Of Block : *
+
+Apertures used:
+
+ Code Shape Size used
+
+ D10 draw 0.0000inch 8
+ D11 draw 0.0100inch 266
+ D12 rectangle 0.1181inch x 0.0787inch 8
+ D13 rectangle 0.0591inch x 0.0236inch 6
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+ D19 rectangle 0.0276inch x 0.0266inch 1
+ D20 rectangle 0.3780inch x 0.0787inch 1
+ D21 draw 0.0236inch 212
+ D22 round 0.0278inch 45
+
diff --git a/hardware/smartcard-fpc/smartcard-fpc.brd b/hardware/smartcard-fpc/smartcard-fpc.brd
new file mode 100644
index 0000000..c1bd3d4
--- /dev/null
+++ b/hardware/smartcard-fpc/smartcard-fpc.brd
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+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
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+<layer number="254" name="cooling" color="7" fill="1" visible="yes" active="yes"/>
+</layers>
+<board>
+<plain>
+<wire x1="0" y1="50.32" x2="0" y2="3.18" width="0" layer="20"/>
+<wire x1="0" y1="3.18" x2="3.18" y2="0" width="0" layer="20" curve="90"/>
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+<text x="50.038" y="47.752" size="1.778" layer="1" font="vector" ratio="14">smart card FPC adapter
+(C) 2020 sysmocom - s.f.m.c. GmbH</text>
+<text x="50.038" y="47.752" size="1.778" layer="25" font="vector" ratio="14">smart card FPC adapter
+(C) 2020 sysmocom - s.f.m.c. GmbH</text>
+<text x="98.806" y="47.752" size="1.778" layer="26" font="vector" ratio="14" rot="MR0">smart card FPC adapter
+(C) 2020 sysmocom - s.f.m.c. GmbH</text>
+<text x="98.806" y="47.752" size="1.778" layer="16" font="vector" ratio="14" rot="MR0">smart card FPC adapter
+(C) 2020 sysmocom - s.f.m.c. GmbH</text>
+</plain>
+<libraries>
+<library name="iso7816-card">
+<packages>
+<package name="ISO7816_CARD">
+<description>Smart Card as per ISO7816-2</description>
+<wire x1="-39.62" y1="27" x2="39.62" y2="27" width="0.127" layer="48"/>
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+</package>
+</packages>
+</library>
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+<description>&lt;b&gt;PCB Matrix Packages&lt;/b&gt;&lt;p&gt;</description>
+<packages>
+<package name="FPC_REBEL_SFW6R-1ST">
+<description>FCI FPC connector SFW6R-1STE1LF
+
+according to Drawing JSA 96336 / revision D, Nov 1, 2009
+
+used in Rebelsim FPC</description>
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+</package>
+<package name="WEEE_BIN_TOP">
+<description>WEEE bin according to Article 11(2) of the WEEE directive</description>
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+</package>
+</packages>
+</library>
+<library name="rc-sysmocom">
+<packages>
+<package name="_0603">
+<description>&lt;b&gt;0603&lt;/b&gt;</description>
+<wire x1="-0.432" y1="-0.306" x2="0.432" y2="-0.306" width="0.1016" layer="51"/>
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+<wire x1="-1.4605" y1="-0.635" x2="-1.4605" y2="0.635" width="0.2032" layer="21"/>
+<smd name="1" x="-0.762" y="0" dx="0.9" dy="0.8" layer="1" roundness="30" cream="no"/>
+<smd name="2" x="0.762" y="0" dx="0.9" dy="0.8" layer="1" roundness="30" cream="no"/>
+<text x="-1.5875" y="0.9525" size="1.016" layer="25" font="vector" ratio="14">&gt;NAME</text>
+<text x="-1.5875" y="-1.4923" size="0.508" layer="27" font="vector" ratio="10">&gt;VALUE</text>
+<rectangle x1="0.4318" y1="-0.4" x2="0.8382" y2="0.4" layer="51"/>
+<rectangle x1="-0.8382" y1="-0.4" x2="-0.4318" y2="0.4" layer="51"/>
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+<vertex x="1.11125" y="-0.3175"/>
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+</package>
+</packages>
+</library>
+<library name="oshw">
+<description>&lt;p&gt;&lt;strong&gt;Open Source Hardware PCB Logos&lt;/strong&gt;
+&lt;p&gt;A simple polygon based version of the OSHWA logos for use on Eagle PCB's
+&lt;p&gt;For use please refer to the OSHWA definition at &lt;a href="http://www.oshwa.org/definition/"&gt;http://www.oshwa.org/definition/&lt;/a&gt;
+&lt;p&gt;Based on the NBitWonder version (&lt;a href="http://nbitwonder.com"&gt;http://nbitwonder.com&lt;/a&gt;)
+&lt;p&gt;&lt;strong&gt;Andrew Cooper&lt;/strong&gt;&lt;br&gt;28Nov2016&lt;br&gt;&lt;a href="http://www.darkerview.com"&gt;www.DarkerView.com&lt;/a&gt;</description>
+<packages>
+<package name="OSHW_8MM">
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+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0.6" drill="0">
+</class>
+</classes>
+<designrules name="default *">
+<description language="de">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+Die Standard-Design-Rules sind so gewählt, dass sie für
+die meisten Anwendungen passen. Sollte ihre Platine
+besondere Anforderungen haben, treffen Sie die erforderlichen
+Einstellungen hier und speichern die Design Rules unter
+einem neuen Namen ab.</description>
+<description language="en">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
+<param name="mtIsolate" value="0.8mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
+<param name="mdWireWire" value="10mil"/>
+<param name="mdWirePad" value="10mil"/>
+<param name="mdWireVia" value="10mil"/>
+<param name="mdPadPad" value="8mil"/>
+<param name="mdPadVia" value="8mil"/>
+<param name="mdViaVia" value="8mil"/>
+<param name="mdSmdPad" value="8mil"/>
+<param name="mdSmdVia" value="8mil"/>
+<param name="mdSmdSmd" value="8mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="40mil"/>
+<param name="mdDrill" value="8mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="10mil"/>
+<param name="msDrill" value="24mil"/>
+<param name="msMicroVia" value="9.99mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="10mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="10mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="10mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="8mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="8mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="4mil"/>
+<param name="mlMaxStopFrame" value="4mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="50"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="AutoGrid" value="1"/>
+<param name="Efforts" value="0"/>
+<param name="TopRouterVariant" value="1"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="a"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="a"/>
+<param name="cfVia" value="8"/>
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+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
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+<param name="cfBase.5" value="1"/>
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+<param name="cfBase.12" value="1"/>
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+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
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+<pass name="Follow-me" refer="Default" active="yes">
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+<pass name="Busses" refer="Default" active="yes">
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+<pass name="Route" refer="Default" active="yes">
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+<wire x1="86.614" y1="30.734" x2="87.36110625" y2="29.98689375" width="0.6" layer="1"/>
+<wire x1="87.36110625" y1="29.98689375" x2="88.0682125" y2="29.694" width="0.6" layer="1" curve="45"/>
+<wire x1="88.0682125" y1="29.694" x2="93.734" y2="29.694" width="0.6" layer="1"/>
+</signal>
+<signal name="IO">
+<contactref element="X1" pad="C7"/>
+<contactref element="X2" pad="4"/>
+<wire x1="18.87" y1="28.6" x2="19.0969375" y2="28.694" width="0.6" layer="1" curve="-45"/>
+<wire x1="19.0969375" y1="28.694" x2="93.734" y2="28.694" width="0.6" layer="1"/>
+</signal>
+</signals>
+</board>
+</drawing>
+<compatibility>
+<note version="6.3" minversion="6.2.2" severity="warning">
+Since Version 6.2.2 text objects can contain more than one line,
+which will not be processed correctly with this version.
+</note>
+</compatibility>
+</eagle>
diff --git a/hardware/smartcard-fpc/smartcard-fpc.sch b/hardware/smartcard-fpc/smartcard-fpc.sch
new file mode 100644
index 0000000..a3fb644
--- /dev/null
+++ b/hardware/smartcard-fpc/smartcard-fpc.sch
@@ -0,0 +1,929 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="7.7.0">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="no" active="no"/>
+<layer number="2" name="Route2" color="1" fill="3" visible="no" active="no"/>
+<layer number="3" name="Route3" color="4" fill="3" visible="no" active="no"/>
+<layer number="4" name="Route4" color="1" fill="4" visible="no" active="no"/>
+<layer number="5" name="Route5" color="4" fill="4" visible="no" active="no"/>
+<layer number="6" name="Route6" color="1" fill="8" visible="no" active="no"/>
+<layer number="7" name="Route7" color="4" fill="8" visible="no" active="no"/>
+<layer number="8" name="Route8" color="1" fill="2" visible="no" active="no"/>
+<layer number="9" name="Route9" color="4" fill="2" visible="no" active="no"/>
+<layer number="10" name="Route10" color="1" fill="7" visible="no" active="no"/>
+<layer number="11" name="Route11" color="4" fill="7" visible="no" active="no"/>
+<layer number="12" name="Route12" color="1" fill="5" visible="no" active="no"/>
+<layer number="13" name="Route13" color="4" fill="5" visible="no" active="no"/>
+<layer number="14" name="Route14" color="1" fill="6" visible="no" active="no"/>
+<layer number="15" name="Route15" color="4" fill="6" visible="no" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="no" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="no" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="no" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="no" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="no" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="no" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="no" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="no" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="no" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="no" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="no" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="no" active="no"/>
+<layer number="50" name="dxf" color="7" fill="1" visible="no" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="no" active="no"/>
+<layer number="53" name="tGND_GNDA" color="7" fill="9" visible="no" active="no"/>
+<layer number="54" name="bGND_GNDA" color="1" fill="9" visible="no" active="no"/>
+<layer number="56" name="wert" color="7" fill="1" visible="no" active="no"/>
+<layer number="57" name="tCAD" color="6" fill="1" visible="no" active="no"/>
+<layer number="59" name="tMark" color="7" fill="1" visible="no" active="no"/>
+<layer number="60" name="bMark" color="7" fill="1" visible="no" active="no"/>
+<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="99" name="SpiceOrder" color="7" fill="1" visible="no" active="no"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="iso7816-card">
+<packages>
+<package name="ISO7816_CARD">
+<description>Smart Card as per ISO7816-2</description>
+<wire x1="-39.62" y1="27" x2="39.62" y2="27" width="0.127" layer="48"/>
+<wire x1="39.62" y1="27" x2="42.8" y2="23.82" width="0.127" layer="48" curve="-90"/>
+<wire x1="42.8" y1="23.82" x2="42.8" y2="-23.82" width="0.127" layer="48"/>
+<wire x1="42.8" y1="-23.82" x2="39.62" y2="-27" width="0.127" layer="48" curve="-90"/>
+<wire x1="39.62" y1="-27" x2="-39.62" y2="-27" width="0.127" layer="48"/>
+<wire x1="-39.62" y1="-27" x2="-42.8" y2="-23.82" width="0.127" layer="48" curve="-90"/>
+<wire x1="-42.8" y1="-23.82" x2="-42.8" y2="23.82" width="0.127" layer="48"/>
+<wire x1="-42.8" y1="23.82" x2="-39.62" y2="27" width="0.127" layer="48" curve="-90"/>
+<smd name="C1" x="-31.55" y="6.92" dx="3" dy="2" layer="1"/>
+<smd name="C2" x="-31.55" y="4.38" dx="3" dy="2" layer="1"/>
+<smd name="C3" x="-31.55" y="1.85" dx="3" dy="2" layer="1"/>
+<smd name="C4" x="-31.55" y="-0.7" dx="3" dy="2" layer="1"/>
+<smd name="C5" x="-23.93" y="6.92" dx="3" dy="2" layer="1"/>
+<smd name="C6" x="-23.93" y="4.38" dx="3" dy="2" layer="1"/>
+<smd name="C7" x="-23.93" y="1.85" dx="3" dy="2" layer="1"/>
+<smd name="C8" x="-23.93" y="-0.7" dx="3" dy="2" layer="1"/>
+<text x="-34.29" y="7.62" size="1.27" layer="21" rot="R180">VCC</text>
+<text x="-34.29" y="5.08" size="1.27" layer="21" rot="R180">RST</text>
+<text x="-34.29" y="2.54" size="1.27" layer="21" rot="R180">CLK</text>
+<text x="-34.29" y="0" size="1.27" layer="21" rot="R180">AUX1</text>
+<text x="-21.59" y="6.35" size="1.27" layer="21">GND</text>
+<text x="-21.59" y="3.81" size="1.27" layer="21">VPP</text>
+<text x="-21.59" y="1.27" size="1.27" layer="21">I/O</text>
+<text x="-21.59" y="-1.27" size="1.27" layer="21">AUX2</text>
+<text x="-30.48" y="10.16" size="1.27" layer="25">&gt;NAME</text>
+</package>
+</packages>
+<symbols>
+<symbol name="SIM">
+<pin name="VCC" x="-15.24" y="5.08" length="middle" direction="pwr"/>
+<pin name="RST" x="-15.24" y="2.54" length="middle" direction="in"/>
+<pin name="CLK" x="-15.24" y="0" length="middle" direction="in"/>
+<pin name="AUX1" x="-15.24" y="-2.54" length="middle"/>
+<pin name="AUX2" x="12.7" y="-2.54" length="middle" rot="R180"/>
+<pin name="I/O" x="12.7" y="0" length="middle" rot="R180"/>
+<pin name="VPP" x="12.7" y="2.54" length="middle" direction="pwr" rot="R180"/>
+<pin name="GND" x="12.7" y="5.08" length="middle" rot="R180"/>
+<wire x1="-1.27" y1="6.35" x2="7.62" y2="6.35" width="0.254" layer="94"/>
+<wire x1="7.62" y1="6.35" x2="7.62" y2="3.81" width="0.254" layer="94"/>
+<wire x1="7.62" y1="1.27" x2="7.62" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-1.27" x2="7.62" y2="-3.81" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-3.81" x2="-1.27" y2="-3.81" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="-3.81" x2="-10.16" y2="-3.81" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="-3.81" x2="-10.16" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="1.27" x2="-10.16" y2="3.81" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="3.81" x2="-10.16" y2="6.35" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="6.35" x2="-1.27" y2="6.35" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="6.35" x2="-1.27" y2="3.81" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="3.81" x2="-2.54" y2="3.81" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="3.81" x2="-2.54" y2="3.81" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="3.81" x2="-2.54" y2="1.27" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="1.27" x2="-2.54" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.27" x2="-1.27" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="-3.81" x2="-1.27" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="-1.27" y1="-1.27" x2="0" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="7.62" y1="-1.27" x2="0" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="0" y1="1.27" x2="0" y2="3.81" width="0.254" layer="94"/>
+<wire x1="0" y1="3.81" x2="7.62" y2="3.81" width="0.254" layer="94"/>
+<wire x1="7.62" y1="3.81" x2="7.62" y2="1.27" width="0.254" layer="94"/>
+<wire x1="7.62" y1="1.27" x2="0" y2="1.27" width="0.254" layer="94"/>
+<wire x1="0" y1="1.27" x2="0" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="-2.54" y1="-1.27" x2="-10.16" y2="-1.27" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="-1.27" x2="-10.16" y2="1.27" width="0.254" layer="94"/>
+<wire x1="-10.16" y1="1.27" x2="-2.54" y2="1.27" width="0.254" layer="94"/>
+<text x="-10.16" y="7.62" size="1.778" layer="95">&gt;NAME</text>
+<text x="-10.16" y="-6.35" size="1.778" layer="96">&gt;VALUE</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="SMARTCARD" prefix="X" uservalue="yes">
+<description>ISO 7916 SMart Card</description>
+<gates>
+<gate name="G1" symbol="SIM" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="ISO7816_CARD">
+<connects>
+<connect gate="G1" pin="AUX1" pad="C4"/>
+<connect gate="G1" pin="AUX2" pad="C8"/>
+<connect gate="G1" pin="CLK" pad="C3"/>
+<connect gate="G1" pin="GND" pad="C5"/>
+<connect gate="G1" pin="I/O" pad="C7"/>
+<connect gate="G1" pin="RST" pad="C2"/>
+<connect gate="G1" pin="VCC" pad="C1"/>
+<connect gate="G1" pin="VPP" pad="C6"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="frames">
+<description>&lt;b&gt;Frames for Sheet and Layout&lt;/b&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="DINA4_L">
+<frame x1="0" y1="0" x2="264.16" y2="180.34" columns="4" rows="4" layer="94" border-left="no" border-top="no" border-right="no" border-bottom="no"/>
+</symbol>
+<symbol name="DOCFIELD">
+<wire x1="0" y1="0" x2="71.12" y2="0" width="0.1016" layer="94"/>
+<wire x1="101.6" y1="15.24" x2="87.63" y2="15.24" width="0.1016" layer="94"/>
+<wire x1="0" y1="0" x2="0" y2="5.08" width="0.1016" layer="94"/>
+<wire x1="0" y1="5.08" x2="71.12" y2="5.08" width="0.1016" layer="94"/>
+<wire x1="0" y1="5.08" x2="0" y2="15.24" width="0.1016" layer="94"/>
+<wire x1="101.6" y1="15.24" x2="101.6" y2="5.08" width="0.1016" layer="94"/>
+<wire x1="71.12" y1="5.08" x2="71.12" y2="0" width="0.1016" layer="94"/>
+<wire x1="71.12" y1="5.08" x2="87.63" y2="5.08" width="0.1016" layer="94"/>
+<wire x1="71.12" y1="0" x2="101.6" y2="0" width="0.1016" layer="94"/>
+<wire x1="87.63" y1="15.24" x2="87.63" y2="5.08" width="0.1016" layer="94"/>
+<wire x1="87.63" y1="15.24" x2="0" y2="15.24" width="0.1016" layer="94"/>
+<wire x1="87.63" y1="5.08" x2="101.6" y2="5.08" width="0.1016" layer="94"/>
+<wire x1="101.6" y1="5.08" x2="101.6" y2="0" width="0.1016" layer="94"/>
+<wire x1="0" y1="15.24" x2="0" y2="22.86" width="0.1016" layer="94"/>
+<wire x1="101.6" y1="35.56" x2="0" y2="35.56" width="0.1016" layer="94"/>
+<wire x1="101.6" y1="35.56" x2="101.6" y2="22.86" width="0.1016" layer="94"/>
+<wire x1="0" y1="22.86" x2="101.6" y2="22.86" width="0.1016" layer="94"/>
+<wire x1="0" y1="22.86" x2="0" y2="35.56" width="0.1016" layer="94"/>
+<wire x1="101.6" y1="22.86" x2="101.6" y2="15.24" width="0.1016" layer="94"/>
+<text x="1.27" y="1.27" size="2.54" layer="94">Date:</text>
+<text x="12.7" y="1.27" size="2.54" layer="94">&gt;LAST_DATE_TIME</text>
+<text x="72.39" y="1.27" size="2.54" layer="94">Sheet:</text>
+<text x="86.36" y="1.27" size="2.54" layer="94">&gt;SHEET</text>
+<text x="88.9" y="11.43" size="2.54" layer="94">REV:</text>
+<text x="1.27" y="19.05" size="2.54" layer="94">TITLE:</text>
+<text x="1.27" y="11.43" size="2.54" layer="94">Document Number:</text>
+<text x="17.78" y="19.05" size="2.54" layer="94">&gt;DRAWING_NAME</text>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="DINA4_L" prefix="FRAME" uservalue="yes">
+<description>&lt;b&gt;FRAME&lt;/b&gt;&lt;p&gt;
+DIN A4, landscape with extra doc field</description>
+<gates>
+<gate name="G$1" symbol="DINA4_L" x="0" y="0"/>
+<gate name="G$2" symbol="DOCFIELD" x="162.56" y="0" addlevel="must"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="laforge">
+<description>&lt;b&gt;PCB Matrix Packages&lt;/b&gt;&lt;p&gt;</description>
+<packages>
+<package name="FPC_REBEL_SFW6R-1ST">
+<description>FCI FPC connector SFW6R-1STE1LF
+
+according to Drawing JSA 96336 / revision D, Nov 1, 2009
+
+used in Rebelsim FPC</description>
+<smd name="6" x="2.5" y="0.5" dx="0.6" dy="1.5" layer="1"/>
+<smd name="5" x="1.5" y="0.5" dx="0.6" dy="1.5" layer="1"/>
+<smd name="4" x="0.5" y="0.5" dx="0.6" dy="1.5" layer="1"/>
+<smd name="3" x="-0.5" y="0.5" dx="0.6" dy="1.5" layer="1"/>
+<smd name="2" x="-1.5" y="0.5" dx="0.6" dy="1.5" layer="1"/>
+<smd name="1" x="-2.5" y="0.5" dx="0.6" dy="1.5" layer="1"/>
+<smd name="M1" x="-3.5" y="-1.6" dx="0.7" dy="4.2" layer="1"/>
+<smd name="M2" x="3.5" y="-1.6" dx="0.7" dy="4.2" layer="1"/>
+<wire x1="5.9" y1="-4.3" x2="5.3" y2="-4.3" width="0.127" layer="21"/>
+<wire x1="5.3" y1="-4.3" x2="-5.3" y2="-4.3" width="0.127" layer="21"/>
+<wire x1="-5.3" y1="-4.3" x2="-5.9" y2="-4.3" width="0.127" layer="21"/>
+<wire x1="5.9" y1="-5.5" x2="-5.9" y2="-5.5" width="0.127" layer="21"/>
+<wire x1="-5.9" y1="-4.3" x2="-5.9" y2="-5.5" width="0.127" layer="21"/>
+<wire x1="5.9" y1="-4.3" x2="5.9" y2="-5.5" width="0.127" layer="21"/>
+<wire x1="-5.3" y1="0" x2="5.3" y2="0" width="0.127" layer="21"/>
+<wire x1="-5.3" y1="0" x2="-5.3" y2="-4.3" width="0.127" layer="21"/>
+<wire x1="5.3" y1="0" x2="5.3" y2="-4.3" width="0.127" layer="21"/>
+<text x="7.62" y="-5.08" size="1.27" layer="25" font="vector" ratio="14" rot="R90">&gt;NAME</text>
+</package>
+<package name="FPC_SODLER_6">
+<smd name="6" x="2.5" y="0.5" dx="0.6" dy="2.5" layer="1"/>
+<smd name="5" x="1.5" y="0.5" dx="0.6" dy="2.5" layer="1"/>
+<smd name="4" x="0.5" y="0.5" dx="0.6" dy="2.5" layer="1"/>
+<smd name="3" x="-0.5" y="0.5" dx="0.6" dy="2.5" layer="1"/>
+<smd name="2" x="-1.5" y="0.5" dx="0.6" dy="2.5" layer="1"/>
+<smd name="1" x="-2.5" y="0.5" dx="0.6" dy="2.5" layer="1"/>
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+<rectangle x1="-1" y1="-0.65" x2="-0.4168" y2="0.65" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.5001" x2="0.1999" y2="0.5001" layer="35"/>
+</package>
+<package name="C1808">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt;
+High volt MLC; no solder stop between for higher isolation&lt;br&gt;
+Source: http://www.avx.com/docs/catalogs/aphvc.pdf</description>
+<wire x1="-1.4732" y1="0.9502" x2="1.4732" y2="0.9502" width="0.1016" layer="51"/>
+<wire x1="-1.4478" y1="-0.9502" x2="1.4732" y2="-0.9502" width="0.1016" layer="51"/>
+<smd name="1" x="-1.95" y="0" dx="1.6" dy="2.2" layer="1" roundness="30" cream="no"/>
+<smd name="2" x="1.95" y="0" dx="1.6" dy="2.2" layer="1" roundness="30" cream="no"/>
+<text x="-2.233" y="1.827" size="1.016" layer="25" font="vector" ratio="10">&gt;NAME</text>
+<text x="-2.233" y="-2.842" size="1.016" layer="27" font="vector" ratio="10">&gt;VALUE</text>
+<rectangle x1="-2.275" y1="-1.015" x2="-1.225" y2="1.015" layer="51"/>
+<rectangle x1="1.225" y1="-1.015" x2="2.275" y2="1.015" layer="51"/>
+<wire x1="-2.8575" y1="1.27" x2="2.8575" y2="1.27" width="0.06" layer="39"/>
+<wire x1="2.8575" y1="1.27" x2="2.8575" y2="-1.27" width="0.06" layer="39"/>
+<wire x1="2.8575" y1="-1.27" x2="-2.8575" y2="-1.27" width="0.06" layer="39"/>
+<wire x1="-2.8575" y1="-1.27" x2="-2.8575" y2="1.27" width="0.06" layer="39"/>
+<polygon width="0.1" layer="29">
+<vertex x="-0.9525" y="1.27"/>
+<vertex x="0.9525" y="1.27"/>
+<vertex x="0.9525" y="-1.27"/>
+<vertex x="-0.9525" y="-1.27"/>
+</polygon>
+<polygon width="0.2" layer="31">
+<vertex x="-2.619375" y="0.9525"/>
+<vertex x="-2.619375" y="-0.9525"/>
+<vertex x="-1.74625" y="-0.9525"/>
+<vertex x="-1.27" y="0"/>
+<vertex x="-1.74625" y="0.9525"/>
+</polygon>
+<polygon width="0.2" layer="31">
+<vertex x="1.27" y="0"/>
+<vertex x="1.74625" y="0.9525"/>
+<vertex x="2.54" y="0.9525"/>
+<vertex x="2.54" y="-0.9525"/>
+<vertex x="1.74625" y="-0.9525"/>
+</polygon>
+</package>
+<package name="C1210">
+<description>&lt;b&gt;CAPACITOR&lt;/b&gt;&lt;p&gt; chip</description>
+<wire x1="-2.473" y1="1.483" x2="2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="2.473" y1="-1.483" x2="-2.473" y2="-1.483" width="0.0508" layer="39"/>
+<wire x1="-2.473" y1="-1.483" x2="-2.473" y2="1.483" width="0.0508" layer="39"/>
+<wire x1="-0.9652" y1="1.2446" x2="0.9652" y2="1.2446" width="0.1016" layer="51"/>
+<wire x1="-0.9652" y1="-1.2446" x2="0.9652" y2="-1.2446" width="0.1016" layer="51"/>
+<wire x1="2.473" y1="1.483" x2="2.473" y2="-1.483" width="0.0508" layer="39"/>
+<smd name="1" x="-1.4" y="0" dx="1.6" dy="2.7" layer="1" roundness="30" cream="no"/>
+<smd name="2" x="1.4" y="0" dx="1.6" dy="2.7" layer="1" roundness="30" cream="no"/>
+<text x="-1.397" y="1.651" size="1.016" layer="25" font="vector" ratio="14">&gt;NAME</text>
+<text x="-1.397" y="-2.921" size="0.508" layer="27" font="vector" ratio="10">&gt;VALUE</text>
+<rectangle x1="-1.7018" y1="-1.2954" x2="-0.9517" y2="1.3045" layer="51"/>
+<rectangle x1="0.9517" y1="-1.3045" x2="1.7018" y2="1.2954" layer="51"/>
+<rectangle x1="-0.1999" y1="-0.4001" x2="0.1999" y2="0.4001" layer="35"/>
+<polygon width="0.2" layer="31">
+<vertex x="-2.06375" y="1.190625"/>
+<vertex x="-2.06375" y="-1.190625"/>
+<vertex x="-1.11125" y="-1.190625"/>
+<vertex x="-0.635" y="0"/>
+<vertex x="-1.11125" y="1.190625"/>
+</polygon>
+<polygon width="0.2" layer="31">
+<vertex x="0.635" y="0"/>
+<vertex x="1.11125" y="1.190625"/>
+<vertex x="2.06375" y="1.190625"/>
+<vertex x="2.06375" y="-1.190625"/>
+<vertex x="1.11125" y="-1.190625"/>
+</polygon>
+</package>
+<package name="C1812K">
+<description>&lt;b&gt;Ceramic Chip Capacitor KEMET 1812 reflow solder&lt;/b&gt;&lt;p&gt;
+Metric Code Size 4532</description>
+<wire x1="-2.175" y1="1.525" x2="2.175" y2="1.525" width="0.1016" layer="51"/>
+<wire x1="2.175" y1="-1.525" x2="-2.175" y2="-1.525" width="0.1016" layer="51"/>
+<smd name="1" x="-2.05" y="0" dx="1.8" dy="3.7" layer="1" roundness="30" cream="no"/>
+<smd name="2" x="2.05" y="0" dx="1.8" dy="3.7" layer="1" roundness="30" cream="no"/>
+<text x="-2.25" y="2.10875" size="1.016" layer="25" ratio="17">&gt;NAME</text>
+<text x="-2.25" y="-3.13375" size="1.016" layer="27" ratio="17">&gt;VALUE</text>
+<rectangle x1="-2.25" y1="-1.6" x2="-1.65" y2="1.6" layer="51"/>
+<rectangle x1="1.65" y1="-1.6" x2="2.25" y2="1.6" layer="51"/>
+<polygon width="0.4064" layer="31">
+<vertex x="-2.69875" y="1.5875"/>
+<vertex x="-1.905" y="1.5875"/>
+<vertex x="-1.27" y="0"/>
+<vertex x="-1.905" y="-1.5875"/>
+<vertex x="-2.69875" y="-1.5875"/>
+</polygon>
+<polygon width="0.4064" layer="31">
+<vertex x="1.27" y="0"/>
+<vertex x="1.905" y="1.5875"/>
+<vertex x="2.69875" y="1.5875"/>
+<vertex x="2.69875" y="-1.5875"/>
+<vertex x="1.905" y="-1.5875"/>
+</polygon>
+</package>
+</packages>
+<symbols>
+<symbol name="CAPACITOR">
+<wire x1="1.778" y1="0" x2="2.54" y2="0" width="0.1524" layer="94"/>
+<wire x1="0" y1="0" x2="0.762" y2="0" width="0.1524" layer="94"/>
+<text x="-1.524" y="2.54" size="1.27" layer="95">&gt;NAME</text>
+<text x="-1.524" y="-3.556" size="1.27" layer="96">&gt;VALUE</text>
+<rectangle x1="0.508" y1="-0.254" x2="3.048" y2="0.254" layer="94" rot="R90"/>
+<rectangle x1="-0.508" y1="-0.254" x2="2.032" y2="0.254" layer="94" rot="R90"/>
+<pin name="1" x="-2.54" y="0" visible="off" length="short" direction="pas" swaplevel="1"/>
+<pin name="2" x="5.08" y="0" visible="off" length="short" direction="pas" swaplevel="1" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="CAP_CERAMIC" prefix="C" uservalue="yes">
+<description>&lt;p&gt;&lt;b&gt;Ceramic Capacitors&lt;/b&gt;&lt;/p&gt;
+&lt;b&gt;0402&lt;/b&gt; - 0402 Surface Mount Capacitors
+&lt;ul&gt;
+&lt;li&gt;16pF 50V 5% [Digikey: 445-4899-2-ND]&lt;/li&gt;
+&lt;li&gt;18pF 50V 5% [Digikey: 490-1281-2-ND]&lt;/li&gt;
+&lt;li&gt;22pF 50V 5% [Digikey: 490-1283-2-ND]&lt;/li&gt;
+&lt;li&gt;68pF 50V 5% [Digikey: 490-1289-2-ND]&lt;/li&gt;
+&lt;li&gt;0.1uF 10V 10% [Digikey: 490-1318-2-ND]&lt;/li&gt;
+&lt;li&gt;1.0uF 6.3V 10% [Digikey: 490-1320-2-ND]&lt;/li&gt;
+&lt;/ul&gt;
+&lt;b&gt;0603&lt;/b&gt; - 0603 Surface Mount Capacitors
+&lt;ul&gt;
+&lt;li&gt;16 pF 50V 5% [Digikey: 445-5051-2-ND]&lt;/li&gt;
+&lt;li&gt;22 pF 50V [Digikey: PCC220ACVTR-ND]&lt;/li&gt;
+&lt;li&gt;33 pF 50V 5% [Digikey: 490-1415-1-ND]&lt;/li&gt;
+&lt;li&gt;56pF 50V 5% [Digikey: 490-1421-1-ND]&lt;/li&gt;
+&lt;li&gt;220pF 50V 5% [Digikey: 445-1285-1-ND]&lt;/li&gt;
+&lt;li&gt;680 pF 50V &lt;/li&gt;
+&lt;li&gt;2200 pF 50V 5% C0G [Digikey: 445-1297-1-ND]&lt;/li&gt;
+&lt;li&gt;5600 pF 100V 5% X7R [Digikey: 478-3711-1-ND]&lt;/li&gt;
+&lt;li&gt;0.1 µF 25V 10% [Digikey: PCC2277TR-ND]&lt;/li&gt;
+&lt;li&gt;0.22 µF 16V 10% X7R [Digikey: 445-1318-1-ND]&lt;/li&gt;
+&lt;li&gt;1.0 µF 25V 10% [Digikey: 445-5146-2-ND]&lt;/li&gt;
+&lt;/ul&gt;
+&lt;b&gt;0603&lt;/b&gt; - RF Specific
+&lt;ul&gt;
+&lt;li&gt;3pF 250V +/-0.1pF RF [Digikey: 712-1347-1-ND]&lt;/li&gt;
+&lt;li&gt;18 pF 250V 5% [Digikey: 478-3505-1-ND or 712-1322-1-ND]&lt;/li&gt;
+&lt;li&gt;56 pF 250V 5% C0G RF [Digikey: 490-4867-1-ND]&lt;/li&gt;
+&lt;li&gt;68 pF 250V RF [Digikey: 490-4868-1-ND]&lt;/li&gt;
+&lt;/ul&gt;
+&lt;b&gt;0805&lt;/b&gt; - 0805 Surface Mount Capacitors
+&lt;ul&gt;
+&lt;li&gt;220 pF 250V 2% &lt;strong&gt;RF&lt;/strong&gt; Ceramic Capacitor [Digikey: 712-1398-1-ND]&lt;/li&gt;
+&lt;li&gt;1000 pF 50V 2% NP0 Ceramic Capacitor [Digikey: 478-3760-1-ND]&lt;/li&gt;
+&lt;li&gt;0.1 µF 25V 10% Ceramic Capacitor [Digikey: PCC1828TR-ND]&lt;/li&gt;
+&lt;li&gt;1.0 µF 16V 10% Ceramic Capacitor[Digikey: 490-1691-2-ND]&lt;/li&gt;
+&lt;li&gt;10.0 µF 10V 10% Ceramic Capacitor[Digikey: 709-1228-1-ND]&lt;/li&gt;
+&lt;li&gt;10.0 uF 16V 10% Ceramic Capacitor [Digikey: 478-5165-2-ND]&lt;/li&gt;
+&lt;li&gt;47 uF 6.3V 20% Ceramic Capacitor [Digikey: 587-1779-1-ND or 399-5506-1-ND]&lt;/li&gt;
+&lt;/ul&gt;
+&lt;/ul&gt;&lt;b&gt;1206&lt;/b&gt; - 1206 Surface Mount Capacitors
+&lt;ul&gt;
+&lt;li&gt;47uF 10V 20% Ceramic Capacitor [Digikey: 490-5528-1-ND or 399-5508-1-ND or 445-6010-1-ND]&lt;/li&gt;
+&lt;li&gt;100uF 6.3V -20%, +80% Y5V Ceramic Capacitor (Digikey: 490-4512-1-ND, Mouser: 81-GRM31CF50J107ZE1L)&lt;/li&gt;
+&lt;/ul&gt;
+&lt;b&gt;1810&lt;/b&gt; - 1810 Surface Mount Capacitors&lt;br&gt;
+High volt MLC; no solder stop between for higher isolation</description>
+<gates>
+<gate name="G$1" symbol="CAPACITOR" x="0" y="-2.54"/>
+</gates>
+<devices>
+<device name="0805" package="0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1206" package="1206">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0603" package="0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="0402" package="0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0402" package="_0402">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0402MP" package="_0402MP">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0603" package="_0603">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0603MP" package="_0603MP">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0805" package="_0805">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="_0805MP" package="_0805MP">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="CAP_HV_1808" package="C1808">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="1210" package="C1210">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+<device name="-C1812" package="C1812K">
+<connects>
+<connect gate="G$1" pin="1" pad="1"/>
+<connect gate="G$1" pin="2" pad="2"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0.6" drill="0">
+</class>
+</classes>
+<parts>
+<part name="X1" library="iso7816-card" deviceset="SMARTCARD" device=""/>
+<part name="FRAME1" library="frames" deviceset="DINA4_L" device=""/>
+<part name="X2" library="laforge" deviceset="FCI_FPC_REBEL_SFW6R-1" device=""/>
+<part name="C1" library="rc-sysmocom" deviceset="CAP_CERAMIC" device="_0603"/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+</plain>
+<instances>
+<instance part="X1" gate="G1" x="43.18" y="78.74"/>
+<instance part="FRAME1" gate="G$1" x="0" y="0"/>
+<instance part="FRAME1" gate="G$2" x="162.56" y="0"/>
+<instance part="X2" gate="G$1" x="99.06" y="83.82"/>
+<instance part="C1" gate="G$1" x="86.36" y="96.52" rot="R180"/>
+</instances>
+<busses>
+</busses>
+<nets>
+<net name="VCC" class="0">
+<segment>
+<pinref part="X2" gate="G$1" pin="VCC"/>
+<wire x1="96.52" y1="91.44" x2="81.28" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="81.28" y1="91.44" x2="25.4" y2="91.44" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="91.44" x2="25.4" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G1" pin="VCC"/>
+<wire x1="25.4" y1="83.82" x2="27.94" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="C1" gate="G$1" pin="2"/>
+<wire x1="81.28" y1="96.52" x2="81.28" y2="91.44" width="0.1524" layer="91"/>
+<junction x="81.28" y="91.44"/>
+</segment>
+</net>
+<net name="RST" class="0">
+<segment>
+<pinref part="X2" gate="G$1" pin="!RST"/>
+<wire x1="96.52" y1="88.9" x2="22.86" y2="88.9" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="88.9" x2="22.86" y2="81.28" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G1" pin="RST"/>
+<wire x1="22.86" y1="81.28" x2="27.94" y2="81.28" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="CLK" class="0">
+<segment>
+<pinref part="X2" gate="G$1" pin="CLK"/>
+<wire x1="96.52" y1="86.36" x2="20.32" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="86.36" x2="20.32" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="X1" gate="G1" pin="CLK"/>
+<wire x1="20.32" y1="78.74" x2="27.94" y2="78.74" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="GND" class="0">
+<segment>
+<pinref part="X1" gate="G1" pin="GND"/>
+<wire x1="55.88" y1="83.82" x2="68.58" y2="83.82" width="0.1524" layer="91"/>
+<wire x1="68.58" y1="83.82" x2="68.58" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="X2" gate="G$1" pin="GND"/>
+<wire x1="68.58" y1="78.74" x2="88.9" y2="78.74" width="0.1524" layer="91"/>
+<pinref part="C1" gate="G$1" pin="1"/>
+<wire x1="88.9" y1="78.74" x2="96.52" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="88.9" y1="96.52" x2="88.9" y2="78.74" width="0.1524" layer="91"/>
+<junction x="88.9" y="78.74"/>
+</segment>
+</net>
+<net name="VPP" class="0">
+<segment>
+<pinref part="X1" gate="G1" pin="VPP"/>
+<pinref part="X2" gate="G$1" pin="VPP"/>
+<wire x1="55.88" y1="81.28" x2="96.52" y2="81.28" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="IO" class="0">
+<segment>
+<pinref part="X1" gate="G1" pin="I/O"/>
+<wire x1="55.88" y1="78.74" x2="66.04" y2="78.74" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="78.74" x2="66.04" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="66.04" y1="76.2" x2="78.74" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="78.74" y1="76.2" x2="78.74" y2="83.82" width="0.1524" layer="91"/>
+<pinref part="X2" gate="G$1" pin="I/O"/>
+<wire x1="78.74" y1="83.82" x2="96.52" y2="83.82" width="0.1524" layer="91"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+</eagle>