From a943a2ed257db0c913e81b04486656ce9382b8bd Mon Sep 17 00:00:00 2001 From: Steve Markgraf Date: Wed, 19 Sep 2012 03:15:43 +0200 Subject: tuner_fc001x: check if PLL values are within boundaries This fixes the issue of the FC0013 locking up at frequencies between 928.0 and 950.0 MHz, which happened because the numerator of the fraction exceeded its 5 bit limit. For the tuner to behave normally again, the dongle needed to be replugged. For the FC0013 this now results in a small gap between 948.6 MHz and 950.0 MHz, where no valid PLL values are existant. For the FC0012 tuning is aborted when the maximum frequency has been reached (948.6 MHz). Signed-off-by: Steve Markgraf --- src/tuner_fc0013.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'src/tuner_fc0013.c') diff --git a/src/tuner_fc0013.c b/src/tuner_fc0013.c index 5423941..76e4b68 100644 --- a/src/tuner_fc0013.c +++ b/src/tuner_fc0013.c @@ -25,6 +25,7 @@ */ #include +#include #include "rtlsdr_i2c.h" #include "tuner_fc0013.h" @@ -320,12 +321,23 @@ int fc0013_set_params(void *dev, uint32_t freq, uint32_t bandwidth) am = (uint8_t)(xdiv - (8 * pm)); if (am < 2) { - reg[1] = am + 8; - reg[2] = pm - 1; + am += 8; + pm--; + } + + if (pm > 31) { + reg[1] = am + (8 * (pm - 31)); + reg[2] = 31; } else { reg[1] = am; reg[2] = pm; } + + if (reg[1] > 15) { + fprintf(stderr, "[FC0013] no valid PLL combination " + "found for %u Hz!\n", freq); + return -1; + } } else { /* fix for frequency less than 45 MHz */ reg[1] = 0x06; -- cgit v1.2.3