From d4c430a80f000d722bb70287af4d4c184a8d7006 Mon Sep 17 00:00:00 2001 From: Paul Brook Date: Wed, 17 Mar 2010 02:14:28 +0000 Subject: Large page TLB flush QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook --- target-microblaze/helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'target-microblaze') diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index d99840c73..5230b52c1 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -76,8 +76,8 @@ int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw, DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n", mmu_idx, vaddr, paddr, lu.prot)); - r = tlb_set_page(env, vaddr, - paddr, lu.prot, mmu_idx, is_softmmu); + tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + r = 0; } else { env->sregs[SR_EAR] = address; DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address)); @@ -107,7 +107,8 @@ int cpu_mb_handle_mmu_fault (CPUState *env, target_ulong address, int rw, /* MMU disabled or not available. */ address &= TARGET_PAGE_MASK; prot = PAGE_BITS; - r = tlb_set_page(env, address, address, prot, mmu_idx, is_softmmu); + tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE); + r = 0; } return r; } -- cgit v1.2.3