aboutsummaryrefslogtreecommitdiffstats
path: root/tcg/ppc
AgeCommit message (Collapse)AuthorFilesLines
2010-04-18tcg/ppc: Remove redundant comparison from brcond2malc1-2/+1
Signed-off-by: malc <av1474@comtv.ru>
2010-04-17tcg/ppc: Fix signed versions of brcond2malc1-1/+2
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber. Signed-off-by: malc <av1474@comtv.ru>
2010-04-06tcg/ppc: Fix typomalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2010-04-06tcg/ppc: Implment bswap16/32malc2-2/+77
Signed-off-by: malc <av1474@comtv.ru>
2010-04-05tcg/ppc: Implement eqv, nand and normalc2-3/+17
Signed-off-by: malc <av1474@comtv.ru>
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-10/+2
Historically the qemu tlb "addend" field was used for both RAM and IO accesses, so needed to be able to hold both host addresses (unsigned long) and guest physical addresses (target_phys_addr_t). However since the introduction of the iotlb field it has only been used for RAM accesses. This means we can change the type of addend to unsigned long, and remove associated hacks in the big-endian TCG backends. We can also remove the host dependence from target_phys_addr_t. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-04tcg/ppc: Fix not_i32malc1-1/+1
Thanks to Alexander Graf for bug report and a good reproducible test case. Signed-off-by: malc <av1474@comtv.ru>
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-3/+3
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operands sign-extended in 64-bit registers (regardless of the "real" sign of the operand). For that, we need to be able to distinguish between a 32-bit load with a 32-bit result and a 32-bit load with a given extension to a 64-bit result. This distinction already exists for the ld* loads, but not the qemu_ld* loads. Reserve qemu_ld32u for 64-bit outputs and introduce qemu_ld32 for 32-bit outputs. Adjust all code generators to match. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-3/+4
Use the TCGCond enumeration type in the brcond and setcond related prototypes in tcg-op.h and each code generator. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
Give the enumeration formed from tcg-opc.h a name: TCGOpcode. Use that enumeration type instead of "int" whereever appropriate. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc1-0/+3
Signed-off-by: malc <av1474@comtv.ru>
2010-02-27tcg/ppc: Fix right rotationmalc1-1/+2
Signed-off-by: malc <av1474@comtv.ru>
2010-02-23tcg/ppc: Fix typomalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg/ppc: Implement some of the optional opsmalc2-8/+88
Signed-off-by: malc <av1474@comtv.ru>
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad1-2/+0
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64. Signed-off-by: Jay Foad <jay.foad@gmail.com> Signed-off-by: malc <av1474@comtv.ru>
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-1/+9
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc1-12/+12
Signed-off-by: malc <av1474@comtv.ru>
2010-02-20Use ppc host calling convention definitions to set ↵Juergen Lock1-3/+3
TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. New version after malc's comments. (This avoids having to do #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__ for the third case.) Submitted by: Andreas Tobler <andreast@fgznet.ch> (original version) Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: proper setcond implementationmalc1-25/+25
Signed-off-by: malc <av1474@comtv.ru>
2010-02-07tcg/ppc32: implement setcond[2]malc1-14/+157
Signed-off-by: malc <av1474@comtv.ru>
2009-09-27tcg/ppc: always use tcg_out_callmalc1-20/+10
Signed-off-by: malc <av1474@comtv.ru>
2009-09-06When targeting PPU use rlwinm instead of andi. if possiblemalc1-8/+54
andi. is microcoded and slow there. Signed-off-by: malc <av1474@comtv.ru>
2009-07-20Fix rbase initializationmalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18PPC 32/64 GUEST_BASE supportmalc2-21/+65
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18Fix LHZX opcode valuemalc1-1/+1
Signed-off-by: malc <av1474@comtv.ru>
2009-04-11Whack [LS]MWmalc1-3/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-3/+0
Noticed by Andreas Faerber git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08Prune unused TCG_AREGsblueswir11-1/+0
Remove definitions for TCG_AREGs corresponding to AREG definitions removed in r6778. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-11Add missing r24..r26 to calle save registersmalc1-0/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26R13 is reserved for small data area pointer by SVR4 PPC ABImalc1-0/+5
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-1/+1
Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-10Introduce and use cache-utils.[ch]malc1-21/+0
Thanks to Segher Boessenkool and Holis Blanchard. AIX and Darwin cache inquiry: http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html Auxiliary vectors: http://manugarg.googlepages.com/aboutelfauxiliaryvectors git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-18Preliminary AIX supportmalc2-2/+52
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-12Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSETmalc1-4/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir11-0/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22Avoid clobbering input register in qemu_ld64+bswap+useronly casemalc1-13/+6
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-9/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-21Relax qemu_ld/st constraints for !SOFTMMU casemalc1-1/+14
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-03Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)malc2-2/+2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-03Preliminary MacOS X on PPC32 supportmalc2-10/+41
Big thanks to BlueSwirl for Sparc failure analysis. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-29On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64malc1-0/+31
Avoids nasty warnings about flush_icache_range from gcc4 and inability to compile [cpu-]exec.c with gcc3 and -O, also the function is much too large to be candidate for inlining anyway. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-28Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc1-64/+38
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-23Provide extNs_M instructionsmalc2-0/+12
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-03Fuse EQ and NE handling in tcg_out_brcond2malc1-7/+4
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-03Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)malc1-1/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
2008-06-23According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatilemalc1-1/+0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-25 17:06:03 +0000