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2010-04-18tcg/ppc: Remove redundant comparison from brcond2malc1-2/+1
2010-04-17tcg/ppc: Fix signed versions of brcond2malc1-1/+2
2010-04-06tcg/ppc: Fix typomalc1-1/+1
2010-04-06tcg/ppc: Implment bswap16/32malc2-2/+77
2010-04-05tcg/ppc: Implement eqv, nand and normalc2-3/+17
2010-04-05Split TLB addend and target_phys_addr_tPaul Brook1-10/+2
2010-04-04tcg/ppc: Fix not_i32malc1-1/+1
2010-03-26tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.Richard Henderson1-3/+3
2010-03-26tcg: Allow target-specific implementation of NOR.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of NAND.Richard Henderson1-0/+1
2010-03-26tcg: Allow target-specific implementation of EQV.Richard Henderson1-0/+1
2010-03-26tcg: Use TCGCond where appropriate.Richard Henderson1-3/+4
2010-03-26tcg: Name the opcode enumeration.Richard Henderson1-1/+1
2010-03-26remove remaining occurrences AREG[1-9] and TCG_AREG[1-9]Paolo Bonzini1-2/+0
2010-03-13tcg/ppc[64]: Only define addend load helpers in softmmu casemalc1-0/+3
2010-02-27tcg/ppc: Fix right rotationmalc1-1/+2
2010-02-23tcg/ppc: Fix typomalc1-1/+1
2010-02-22tcg/ppc: Implement some of the optional opsmalc2-8/+88
2010-02-22tcg: fix build on 32-bit hppa, ppc and sparc hostsJay Foad1-2/+0
2010-02-20tcg: Add comments for all optional instructions not implemented.Richard Henderson1-1/+9
2010-02-20tcg/ppc: Consistently use calling convention selection macrosmalc1-12/+12
2010-02-20Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARG...Juergen Lock1-3/+3
2010-02-07tcg/ppc32: proper setcond implementationmalc1-25/+25
2010-02-07tcg/ppc32: implement setcond[2]malc1-14/+157
2009-09-27tcg/ppc: always use tcg_out_callmalc1-20/+10
2009-09-06When targeting PPU use rlwinm instead of andi. if possiblemalc1-8/+54
2009-07-20Fix rbase initializationmalc1-1/+1
2009-07-18PPC 32/64 GUEST_BASE supportmalc2-21/+65
2009-07-18Fix LHZX opcode valuemalc1-1/+1
2009-04-11Whack [LS]MWmalc1-3/+0
2009-04-11Remove reserved registers from tcg_target_reg_alloc_ordermalc1-3/+0
2009-03-08Prune unused TCG_AREGsblueswir11-1/+0
2009-02-11Add missing r24..r26 to calle save registersmalc1-0/+5
2009-01-26R13 is reserved for small data area pointer by SVR4 PPC ABImalc1-0/+5
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc1-1/+1
2008-12-10Introduce and use cache-utils.[ch]malc1-21/+0
2008-11-18Preliminary AIX supportmalc2-2/+52
2008-11-12Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSETmalc1-4/+4
2008-10-05Add some missing static and const qualifiers, reg_names only used if NDEBUG setblueswir11-0/+2
2008-09-22Avoid clobbering input register in qemu_ld64+bswap+useronly casemalc1-13/+6
2008-08-30Fix some warnings that would be generated by gcc -Wredundant-declsblueswir11-9/+2
2008-08-21Relax qemu_ld/st constraints for !SOFTMMU casemalc1-1/+14
2008-08-03Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)malc2-2/+2
2008-08-03Preliminary MacOS X on PPC32 supportmalc2-10/+41
2008-07-29On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64malc1-0/+31
2008-07-28Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does itmalc1-64/+38
2008-07-23Provide extNs_M instructionsmalc2-0/+12
2008-07-03Fuse EQ and NE handling in tcg_out_brcond2malc1-7/+4
2008-07-03Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)malc1-1/+1
2008-06-23According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatilemalc1-1/+0
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