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path: root/target-sparc/helper.c
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2011-06-26Remove exec-all.h include directivesBlue Swirl1-1/+0
Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26sparc: move do_interrupt to helper.cBlue Swirl1-0/+242
do_interrupt() was mixing CPUState pointer passed from caller and global env (AREG0). Fix by moving the function to helper.c. Introduce a helper for calling change_pstate() safely from outside of execution context. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-08Fix compilation warning due to missing header for sigaction (followup)Alexandre Raymond1-1/+0
This patch removes all references to signal.h when qemu-common.h is included as they become redundant. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-02-01SPARC: Fix Leon3 cache controlFabien Chouteau1-1/+1
The "leon3_cache_control_int" (op_helper.c) function is called within leon3.c which leads to segfault error with the global "env". Now cache control is a CPU feature and everything is handled in op_helper.c. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24SPARC: Add asr17 register supportFabien Chouteau1-1/+2
This register is activated by CPU_FEATURE_ASR17 in the feature field. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-01-24SPARC: Emulation of Leon3Fabien Chouteau1-3/+4
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-19Sparc: implement monitor command 'info tlb'Blue Swirl1-44/+44
Use existing dump_mmu() to implement monitor command 'info tlb'. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-12-03target-sparc: remove unused functions cpu_lock(), cpu_unlock()Peter Maydell1-14/+0
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-7/+4
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-06-02sparc64: fix tag access register on mmu trapsIgor V. Kovalenko1-0/+5
- set mmu tag access register on FAULT and PROT traps as well Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22sparc64: fix mmu context at trap levels above zeroIgor V. Kovalenko1-1/+18
- cpu_mmu_index return MMU_NUCLEUS_IDX if trap level is not zero - cpu_get_tb_cpu_state: store trap level and primary context in flags this allows to restart code translation when address translation is changed - stop translation block after writing to pstate and tl registers - stop translation block after writing to alternate space this can be optimized to stop only if address translation can be changed by write operation (e.g. by comparing with MMU ASI values) Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22sparc64: fix dump_mmu to look for global bit in tte value instead of tagIgor V. Kovalenko1-2/+2
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22sparc64: fix pstate privilege bitsIgor V. Kovalenko1-2/+2
- refactor code to handle hpstate only if available for current cpu - conditionally set hypervisor bit in hpstate register - reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well - disable sparcv8 registers for TARGET_SPARC64 - fix cpu_mmu_index to use sparcv9 bits only Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22sparc64: generate data access exception on RW violationIgor V. Kovalenko1-37/+62
- separate PRIV and PROT handling - DPRINTF_MMU macro to clean up debug code - dump mmu_idx, trap level and mmu context registers along with address translation values Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-22Fix %lld or %llx printf format useBlue Swirl1-2/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-12target-sparc: Fix wrong printf argumentStefan Weil1-1/+1
cpu_get_ccr() returns a target_ulong, so a type cast is needed to avoid wrong output on big endian hosts. We could also use TARGET_FMT_lx, but that would print 8 instead of 2 digits. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-09sparc: Fix lazy flag calculation on interrupts, refactorBlue Swirl1-5/+5
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier flags could be stored to pstate. Refactor PSR/CCR/CWP handling: concentrate the actual functions to op_helper.c. Thanks to Igor Kovalenko for reporting. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-07sparc64: fix build with older gccsBlue Swirl1-0/+1
Fix errors missed in 2065061ede22d401aae2ce995c3af54db9d28639: CC sparc64-softmmu/helper.o cc1: warnings being treated as errors /src/qemu/target-sparc/helper.c: In function 'get_physical_address': /src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function /src/qemu/target-sparc/helper.c:426: note: 'context' was declared here Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-06sparc64: handle asi referencing nucleus and secondary MMU contextsIgor V. Kovalenko1-11/+31
- increase max supported MMU modes to 6 - handle nucleus context asi - handle secondary context asi - handle non-faulting loads from secondary context Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-06sparc64: implement global translation table entries v1Igor V. Kovalenko1-19/+14
- match global tte against any context - show global tte in MMU dump v0->v1: added default case to switch statement in demap_tlb - should fix gcc warning about uninitialized context variable Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-17Large page TLB flushPaul Brook1-14/+26
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-7/+1
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-01-31sparc32 don't mark page dirty when failingArtyom Tarasenko1-5/+6
if the access check fails, the page can not be modified and shouldn't be marked dirty. The patch fixes the "hsfs_putpage: dirty HSFS page" error in Solaris guests. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-17Sparc: improve CPU register dumpBlue Swirl1-30/+55
Common: * Remove unnecessary 0x prefix * Print %y * Fix NZVC flag print order to match CPU bit order Sparc64 specific: * Print registers without line wrapping * Print %f40-%f63 * Pretty print CCR flags * Print %fsr and %fprs in full precision * More consistent formatting Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-13Sparc32: remove unused variable, spotted by clangBlue Swirl1-5/+0
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-08sparc64: add PIL to cpu state dumpIgor V. Kovalenko1-0/+1
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-05Sparc64: handle MMU global bit and nucleus contextBlue Swirl1-11/+19
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-04Sparc64: fix compilation with DEBUG_MMUBlue Swirl1-15/+15
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07user: move CPU reset call to main.c for x86/PPC/SparcBlue Swirl1-3/+0
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07sparc32 (mostly): remove unneeded calls to device resetBlue Swirl1-0/+2
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori1-18/+18
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc1-18/+18
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-18Sparc32/64: Fix user emulator breakageBlue Swirl1-1/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko1-2/+3
tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27sparc64 really implement itlb/dtlb automatic replacement writesIgor Kovalenko1-1/+3
- implement "used" bit in tlb translation entry - mark tlb entry used if qemu code/data translation succeeds - fold i/d mmu replacement writes code into replace_tlb_1bit_lru which adds 1bit lru replacement algorithm; previously code tried to replace first unlocked entry only - extract more bitmasks to named macros - add "immu" or "dmmu" type name to debugging output where appropriate Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-27sparc64 name mmu registers and general cleanupIgor Kovalenko1-28/+40
- add names to mmu registers, this helps understanding the code which uses/modifies them. - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries - extract demap_tlb routine (code duplication) - extract replace_tlb routine (code duplication) - flush qemu tlb translations when replacing sparc64 mmu tlb entries I have no test case which demands flushing qemu translations, and this patch should have no other visible changes to runtime. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-20Fix most warnings (errors with -Werror) when debugging is enabledBlue Swirl1-10/+10
I used the following command to enable debugging: perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/* Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl1-2/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-12sparc64: trap handling correctionsIgor Kovalenko1-0/+4
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote: > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: >> Good trap handling is required to process interrupts. >>  This patch fixes the following: >> >>  - sparc64 has no wim register >>  - sparc64 has no psret register, use IE bit of pstate >>   extract IE checking code to cpu_interrupts_enabled >>  - alternate globals are not available if cpu has GL feature >>   in this case bit AG of pstate is constant zero >>  - write to pstate must actually write pstate >>   even if cpu has GL feature >> >>  Also timer interrupt is handled using do_interrupt. > > A bit too much for one patch. Please also remove the code instead of > commenting out. I now excluded timer interrupt related part. To my mind other changes are essentially tied together. > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32. Fixed, please find attached the updated version. -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: unify mmu tag matching codeIgor Kovalenko1-44/+57
This patch extracts common part of sparc64 tag matching code used by IMMU and DMMU lookups. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: mmu bypass mode correctionIgor Kovalenko1-3/+11
This Implement physical address truncation in mmu bypass mode. IMMU bypass is also active when cpu enters RED_STATE Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-05-13Include assert.h from qemu-common.hPaul Brook1-1/+0
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-10Use dynamical computation for condition codesBlue Swirl1-0/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-02Clarify: dmmuregs[1] is not a typoBlue Swirl1-0/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-04-28sparc64 fix context value for ITLB faultIgor Kovalenko1-1/+1
Revert previous change to get_physical_address_code: I/D MMU context register is shared, so using dmmuregs[1] is correct Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
2009-04-27sparc64 fix TLB match codeIgor Kovalenko1-7/+7
TLB match code must respect page size, otherwise 4M page mappings may be not found. Also correct a typo in get_physical_address_code which should use IMMU registers. Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> -- Kind regards, Igor V. Kovalenko
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori1-0/+1
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir11-2/+3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-21Turn MMUs and caches off on resetblueswir11-0/+1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6636 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori1-2/+0
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
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