aboutsummaryrefslogtreecommitdiffstats
path: root/target-arm
AgeCommit message (Collapse)AuthorFilesLines
2011-03-22target-arm: Fix VRECPS edge cases handlingPeter Maydell1-3/+8
Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: Fix TCG temporary leaks for scalar VMULLPeter Maydell1-0/+2
Fix a TCG temporary leak when translating 32-bit scalar VMULL. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: Set Q bit for overflow in SMUAD and SMLADPeter Maydell1-4/+12
SMUAD and SMLAD are supposed to set the Q bit if the addition of the two 16x16 multiply products and optional accumulator overflows considered as a signed value. However we were only doing this check for the addition of the accumulator, not when adding the products, with the effect that we were mishandling the edge case where both inputs are 0x80008000. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: Fix GE bits for v6media signed modulo arithmeticPeter Maydell1-2/+2
Fix the signed modulo arithmetic helpers for the v6media instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set the GE bits correctly (based on the result of the add or subtract before it is truncated to 16 bits, not after). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: Fix UNDEF cases in Thumb load/storePeter Maydell1-11/+18
Decode of Thumb load/store was merging together the cases of 'bit 11==0' (reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for valid instruction patterns but meant that we would not UNDEF for the cases the architecture mandates that we must. Make the decode actually look at bit 11 as well as [10..8] so that we UNDEF in the right places. This change also removes what was a spurious unreachable 'case 8', and correctly frees TCG temporaries on the illegal-insn codepaths. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-13inline cpu_halted into sole callerPaolo Bonzini1-13/+0
All implementations are now the same, and there is only one caller, so inline the function there. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-03-07target-arm: Implement a minimal set of cp14 debug registersPeter Maydell1-0/+28
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07target-arm: Use TCG temporary leak debugging facilitiesPeter Maydell1-0/+7
Use the new TCG temporary leak debugging facilities to check that each ARM instruction does not leak temporaries. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-07target-arm: Remove ad-hoc leak checking codePeter Maydell1-360/+338
This commit removes the ad-hoc resource leak checking code from target-arm. This includes replacing all uses of new_tmp() with tcg_temp_new_i32() and all uses of dead_tmp() with tcg_temp_free_i32(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski3-3/+50
Implement VA->PA translations by cp15-c7 that went through unchanged previously. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Set carry flag correctly for Thumb2 ORNSPeter Maydell1-2/+1
The code for Thumb2 ORNS (or negated and set flags) was trashing a TCG input register which was needed later for use in calculating flags, with the effect that the carry flag was always set with the wrong sense. Fix this by using the TCG orc op instead of separate not and or ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Handle VMOV between two core and VFP single regsPeter Maydell1-5/+5
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a pair of VFP single precision registers): * An incorrect condition meant these instruction patterns were being treated as load/store multiple, which resulted in the generation of bad code and a runtime segfault * The order of the core register pair was reversed so the values would go to the wrong registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Don't decode old cp15 WFI instructions on v7 coresPeter Maydell1-5/+30
In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class instruction, but in previous versions this functionality was provided via a cp15 coprocessor register. Add correct feature checks to the decoding of the cp15 WFI instructions so that they behave correctly for newer cores. In particular, the old 0,c7,c8,2 encoding used on ARM940 has been reused for VA-to-PA translation in v6 and v7. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24target-arm: fix support for VRSQRTE.Christophe Lyon1-10/+113
Now use the same algorithm as described in the ARM ARM. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24target-arm: fix support for VRECPE.Christophe Lyon1-12/+71
Now use the same algorithm as described in the ARM ARM. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24target-arm: Introduce float64_256 and float64_512 constants.Christophe Lyon1-0/+5
These two constants will be used by helper functions such as recpe_f32 and rsqrte_f32. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-21target-arm: Fix shift by immediate and narrow where src, dest overlapPeter Maydell1-40/+44
For Neon shifts by immediate and narrow, correctly handle the case where the source registers and the destination registers overlap (the second pass should use the original register contents, not the results of the first pass). This includes a refactoring to pull the size check outside the loop rather than inside, since there is now very little common code between the size == 3 and size != 3 case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-21target-arm: Refactor to pull narrowing decode into separate functionPeter Maydell1-26/+19
Pull the code which decodes narrowing operations as being either signed/unsigned saturate or plain out into its own function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix unsigned VQRSHL by large shift countsPeter Maydell1-3/+34
Correctly handle VQRSHL of unsigned values by a shift count of the width of the data type or larger, which must be special-cased in the qrshl_u* helper functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix signed VQRSHL by large shift countsPeter Maydell1-3/+31
Handle the case of signed VQRSHL by a shift count of the width of the data type or larger, which must be special cased in the qrshl_s* helper functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: fix decoding of Neon 64 bit shifts.Christophe Lyon1-15/+30
Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN, VQRSHRN, VQRSHRUN, taking into account whether inputs are unsigned or not. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: fix Neon VQSHRN and VSHRN.Christophe Lyon1-2/+2
Call the normal shift helpers instead of the rounding ones. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix saturated values for Neon right shiftsPeter Maydell1-1/+4
Fix value returned by signed 8 and 16 bit qrshl helpers when the result has saturated. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: fix unsigned 64 bit right shifts.Christophe Lyon1-1/+1
Fix range of shift amounts which always give 0 as result. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix unsigned VRSHL.s8 and .s16 right shifts by type widthChristophe Lyon1-1/+1
Fix handling of unsigned VRSHL.s8 and .s16 right shifts by the type width. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix signed VRSHL by large shift countsPeter Maydell1-14/+3
Correctly handle VRSHL of signed values by a shift count of the width of the data type or larger, which must be special-cased in the rshl_s* helper functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix rounding constant addition for Neon shiftsChristophe Lyon1-12/+127
Handle cases where adding the rounding constant could overflow in Neon shift instructions: VRSHR, VRSRA, VQRSHRN, VQRSHRUN, VRSHRN. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> [peter.maydell@linaro.org: fix handling of large shifts in rshl_s32, calculate signed saturated value as other functions do.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Move Neon VZIP to helper functionsPeter Maydell3-73/+133
Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also give the correct answers where the inline implementation did not. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Move Neon VUZP to helper functionsPeter Maydell3-75/+137
Move the implementation of the Neon VUZP unzip instruction from inline code to helper functions. (At 50+ TCG ops it was well over the recommended limit for coding inline.) The helper implementations also fix the handling of the quadword version of the instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Correct conversion of Thumb Neon dp encodings into ARMJuha Riihimäki1-1/+1
We handle Thumb Neon data processing instructions by converting them into the equivalent ARM encoding, as the two are very close. However the ARM encoding should have bit 28 set, not clear. This wasn't causing any problems because we don't actually look at that bit during decode; however it is better to do the conversion correctly to avoid problems later if we add checks to UNDEF on SBZ/SBO bits. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Fix Neon VQDMLSL instructionPeter Maydell1-8/+14
For VQDMLSL, negation has to occur after saturation, not before. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Refactor handling of VQDMULLPeter Maydell1-10/+6
Refactor the handling of VQDMULL so that it is dealt with in its own if() case rather than together with the accumulating instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-20target-arm: Implement VMULL.P8Peter Maydell3-2/+35
Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply instruction). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-11arm: drop unused irq-related part of CPUARMStateDmitry Eremin-Solenikov1-4/+0
These two fields were added as a part of ARMv7 support patch (back in 2007), were never used by any code, so can be dropped. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2011-02-10target-arm: Remove stray #include from middle of neon_helper.cPeter Maydell1-1/+0
Remove a stray #include <stdio.h> from the middle of neon_helper.c: it was harmless but pointless since we include stdio.h at the top of the file anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10target-arm: Use standard FPSCR for Neon half-precision operationsPeter Maydell3-12/+32
The Neon half-precision conversion operations (VCVT.F16.F32 and VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike the VFP versions (VCVTB and VCVTT). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10target-arm: Silence NaNs resulting from half-precision conversionsPeter Maydell1-2/+10
Silence the NaNs that may result from half-precision conversion, as we do for the other conversions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10softfloat: Add float16 type and float16 NaN handling functionsPeter Maydell1-2/+2
Add a float16 type to softfloat, rather than using bits16 directly. Also add the missing functions float16_is_quiet_nan(), float16_is_signaling_nan() and float16_maybe_silence_nan(), which are needed for the float16 conversion routines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09target-arm: implement vsli.64, vsri.64Christophe Lyon1-1/+13
Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09target-arm: fix VSHLL Neon instruction.Christophe Lyon1-3/+15
Fix bit mask used when widening the result of shift on narrow input. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09target-arm: Fix 32 bit signed saturating narrowPeter Maydell1-1/+1
The returned value when doing saturating signed 64->32 bit conversion of a negative number was incorrect due to a missing cast. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-09target-arm: Fix VQMOVUN Neon instruction.Juha Riihimäki3-6/+88
VQMOVUN does a signed-to-unsigned saturating conversion. This is different from both the signed-to-signed and unsigned-to-unsigned conversions already implemented, so we need a new set of helper functions (neon_unarrow_sat*). Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Fix decoding of Thumb preload and hint spacePeter Maydell1-22/+48
Refine the decoding of the Thumb preload and hint space, so we UNDEF on the patterns that are supposed to UNDEF rather than NOP. We also move the tests for this space earlier, so we don't emit harmless but unnecessary address generation code for preload hints (which by their nature are likely to be in hot code paths). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Fix decoding of preload and memory hint spacePeter Maydell1-3/+25
Correct the decoding of the ARM preload and memory hint space, by adding decoding of PLI, PLDW and the v7MP unallocated hint space. This commit also corrects a slightly overexuberant decoding of PLD(register) which was not checking that bit 4 was one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Clean up handling of MPIDRPeter Maydell1-5/+21
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Add CPU feature flag for v7MPPeter Maydell2-1/+8
Add a CPU feature flag for v7MP (the multiprocessing extensions); some instructions exist only for v7MP and not for the base v7 architecture. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04Set the right overflow bit for neon 32 and 64 bit saturating add/sub.Christophe Lyon4-63/+105
Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Fix Neon vsra instructions.Christophe Lyon1-2/+2
This patch fixes the errors reported by my tests in VSRA. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-29target-arm: Fix Neon VQ(R)DMULH.S16 instructionsJuha Riihimäki1-1/+2
Correct an error in the implementation of the 16 bit forms of VQ(R)DMULH, bringing them into line with the 32 bit implementation. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-26target-arm: Fix loading of scalar value for Neon multiply-by-scalarPeter Maydell1-6/+6
Fix the register and part of register we get the scalar from in the various "multiply vector by scalar" ops (VMUL by scalar and friends). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 17:00:47 +0000