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2011-04-20target-arm: Set Invalid flag for NaN in float-to-int conversionsPeter Maydell1-0/+9
When we catch the special case of an input NaN in ARM float to int helper functions, set the Invalid flag as well as returning the correct result. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-20Implement basic part of SA-1110/SA-1100Dmitry Eremin-Solenikov1-0/+9
Basic implementation of DEC/Intel SA-1100/SA-1110 chips emulation. Implemented: - IRQs - GPIO - PPC - RTC - UARTs (no IrDA/etc.) - OST reused from pxa25x Everything else is TODO (esp. PM/idle/sleep!) - see the todo in the hw/strongarm.c Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17move helpers.h to helper.hLluís1-1/+1
This provides a consistent naming scheme across all targets. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-16Fix some typos in comments and documentationStefan Weil1-1/+1
helpfull -> helpful usefull -> useful cotrol -> control and a grammar fix. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-04-12target-arm: Detect tininess before rounding for FP operationsPeter Maydell1-0/+4
The ARM architecture mandates that we detect tininess before rounding, so set the softfloat fp_status up appropriately. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-10arm: basic support for ARMv4/ARMv4T emulationDmitry Eremin-Solenikov1-1/+28
Currently target-arm/ assumes at least ARMv5 core. Add support for handling also ARMv4/ARMv4T. This changes the following instructions: BX(v4T and later) BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC, MRRC2, PLD QADD, QDADD, QDSUB, QSUB, STRD, SMLAxy, SMLALxy, SMLAWxy, SMULxy, SMULWxy, STC2 (v5 and later) All instructions that are "v5TE and later" are also bound to just v5, as that's how it was before. This patch doesn _not_ include disabling of cp15 access and base-updated data abort model (that will be required to emulate chips based on a ARM7TDMI), because: * no ARM7TDMI chips are currently emulated (or planned) * those features aren't strictly necessary for my purposes (SA-1 core emulation). All v5 models are handled as they are v5T. Internally we still have a check if the model is a v5(T) or v5TE, but as all emulated cores are v5TE, those two cases are simply aliased (for now). Patch is heavily based on patch by Filip Navara <filip.navara@gmail.com> which in turn is based on work by Ulrich Hecht <uli@suse.de> and Vincent Sanders <vince@kyllikki.org>. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-03target-arm/helper.c: For float-int conversion helpers pass ints as intsPeter Maydell1-100/+55
Correct the argument and return types for the float<->int conversion helper functions so that integer arguments and return values are declared as uint32_t/uint64_t, not float32/float64. This allows us to remove the hand-rolled functions which were doing bitwise copies between the types via unions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: use make_float32() to make constant floats for VRSQRTSPeter Maydell1-6/+5
The preferred way to create a constant floating point value is to use make_float32() rather than doing a runtime int32_to_float32(). Convert the code in the VRSQRTS helper to work this way. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: Fix VRECPS edge cases handlingPeter Maydell1-3/+8
Correct the handling of edge cases for the VRECPS instruction: * this is a Neon instruction so uses the "standard FPSCR value" * (zero, inf) is a special case which returns 2.0 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-22target-arm: Fix GE bits for v6media signed modulo arithmeticPeter Maydell1-2/+2
Fix the signed modulo arithmetic helpers for the v6media instructions (SADD8, SSUB8, SADD16, SSUB16, SASX, SSAX) to set the GE bits correctly (based on the result of the add or subtract before it is truncated to 16 bits, not after). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06target-arm: Implement cp15 VA->PA translationAdam Lackorzynski1-2/+46
Implement VA->PA translations by cp15-c7 that went through unchanged previously. Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24target-arm: fix support for VRSQRTE.Christophe Lyon1-10/+113
Now use the same algorithm as described in the ARM ARM. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24target-arm: fix support for VRECPE.Christophe Lyon1-12/+71
Now use the same algorithm as described in the ARM ARM. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-24target-arm: Introduce float64_256 and float64_512 constants.Christophe Lyon1-0/+5
These two constants will be used by helper functions such as recpe_f32 and rsqrte_f32. Signed-off-by: Christophe Lyon <christophe.lyon@st.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10target-arm: Use standard FPSCR for Neon half-precision operationsPeter Maydell1-4/+22
The Neon half-precision conversion operations (VCVT.F16.F32 and VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike the VFP versions (VCVTB and VCVTT). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10target-arm: Silence NaNs resulting from half-precision conversionsPeter Maydell1-2/+10
Silence the NaNs that may result from half-precision conversion, as we do for the other conversions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-10softfloat: Add float16 type and float16 NaN handling functionsPeter Maydell1-2/+2
Add a float16 type to softfloat, rather than using bits16 directly. Also add the missing functions float16_is_quiet_nan(), float16_is_signaling_nan() and float16_maybe_silence_nan(), which are needed for the float16 conversion routines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Clean up handling of MPIDRPeter Maydell1-5/+21
The ARM cp15 register 0,c0,c0,5 is standardised in the v7 architecture as the MPIDR. Clean up its implementation to remove A9 specific handling. This commit includes fixing an error in the value returned for the MPIDR on A9, where we were erroneously claiming a cluster ID of 9. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-02-04target-arm: Add CPU feature flag for v7MPPeter Maydell1-0/+6
Add a CPU feature flag for v7MP (the multiprocessing extensions); some instructions exist only for v7MP and not for the base v7 architecture. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Don't generate code specific to current CPU mode for SRSPeter Maydell1-2/+10
When translating the SRS instruction, handle the "store registers to stack of current mode" case in the helper function rather than inline. This means the generated code does not make assumptions about the current CPU mode which might not be valid when the TB is executed later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Use the standard FPSCR value for VRSQRTSPeter Maydell1-1/+1
VSQRTS always uses the standard FPSCR value as it is a Neon instruction. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Add support for 'Standard FPSCR Value' as used by NeonPeter Maydell1-0/+5
Add support to the ARM helper routines for a second fp_status value which should be used for operations which the ARM ARM indicates use "ARM standard floating-point arithmetic" rather than being controlled by the rounding/flush/NaN settings in the FPSCR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-arm: Fix implementation of VRSQRTSPeter Maydell1-1/+9
The implementation of the ARM VRSQRTS instruction (which calculates (3 - op1 * op2) / 2) was missing the division operation. It also did not handle the special cases of (0,inf) and (inf,0). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: wire up the softfloat flush_input_to_zero flagPeter Maydell1-1/+7
Wire up the new softfloat support for flushing input denormals to zero on ARM. The FPSCR FZ bit enables flush-to-zero for both inputs and outputs, but the reporting of when inputs are flushed to zero is via a separate IDC bit rather than the UFC (underflow) bit used when output denormals are flushed to zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-06target-arm: Set softfloat cumulative exc flags from correct FPSCR bitsPeter Maydell1-1/+1
When handling a write to the ARM FPSCR, set the softfloat cumulative exception flags from the cumulative flags in the FPSCR, not the exception-enable bits. Also don't apply a mask: vfp_exceptbits_to_host will only look at the correct bits anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: correct cp15 c1_sys reset value for arm1136 and cortex-a9Juha Riihimäki1-0/+2
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: correct cp15 c1_sys reset value for cortex-a8Mattias Holm1-0/+1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-27target-arm: fix vmsav6 access controlJuha Riihimäki1-15/+19
Override access control checks (including execute) for mmu translation table descriptors assigned to manager domains. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-12-07ARM: Implement VCVT to 16 bit integer using new softfloat routinesPeter Maydell1-1/+1
Use the softfloat conversion routines for conversion to 16 bit integers, because just casting to a 16 bit type truncates the value rather than saturating it at 16-bit MAXINT/MININT. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Ignore top 16 bits when doing VCVT from 16 bit fixed pointPeter Maydell1-1/+1
VCVT of 16 bit fixed point to float should ignore the top 16 bits of the source register. Cast to int16_t and friends rather than int16 -- the former is guaranteed exactly 16 bits wide where the latter is merely at least 16 bits wide (and so is usually 32 bits). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for single<->double conversion of NaNPeter Maydell1-2/+10
The ARM ARM defines that if the input to a single<->double conversion is a NaN then the output is always forced to be a quiet NaN by setting the most significant bit of the fraction part. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-07ARM: Return correct result for float-to-integer conversion of NaNPeter Maydell1-0/+27
The ARM architecture mandates that converting a NaN value to integer gives zero (if Invalid Operation FP exceptions are not being trapped). This isn't the behaviour of the SoftFloat library, so NaNs must be special-cased. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com>
2010-12-03ARM: Expose vfp_get_fpscr() and vfp_set_fpscr() to C codePeter Maydell1-0/+10
Expose the vfp_get_fpscr() and vfp_set_fpscr() functions to C code as well as generated code, so we can use them to read and write the FPSCR when saving and restoring VFP registers across signal handlers in linux-user mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2010-12-03ARM: enable XScale/iWMMXT in linux-user modePeter Maydell1-0/+6
In linux-user mode, the XScale/iWMMXT coprocessors must be enabled at reset so that we can run code that uses these instructions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2010-10-30target-xxx: Use fprintf_function (format checking)Stefan Weil1-1/+1
fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-01target-arm : fix parallel saturated subtraction implementationChih-Min Chao1-2/+2
Signed-off-by: Chih-Min Chao <cmchao@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-05-31arm: fix arm kernel boot for non zero start addrLars Munch1-1/+0
Booting an arm kernel has been broken a while when booting from non zero start address. This is due to the order of events: board init loads the kernel and sets register 15 to the start address and then qemu_system_reset reset the cpu making register 15 zero again. This patch fixes the usage of the register 15 start address trick in combination with arm_load_kernel. Signed-off-by: Lars Munch <lars@segv.dk> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-05Fix arm-linux-userPaul Brook1-0/+2
Only include hw/loader.h from target-arm/helper.c when building for system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-04-05ARMv7-M reset fixesPaul Brook1-9/+24
Move ARMv7-M PC/SP initialization to the CPU reset routine. Add a board reset routine to call this. Also load values directly from ROM as images have not been copied yet. Avoid clearing the NVIC pointer on cpu reset. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-27target-arm: disable PAGE_EXEC for XN pagesRabin Vincent1-3/+7
Don't set PAGE_EXEC for XN pages, to avoid a bypass of XN protection checking if the page is already in the TLB. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-17Large page TLB flushPaul Brook1-21/+27
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook1-5/+0
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-02-19target-arm: support thumb exception handlersRabin Vincent1-3/+2
When handling an exception, switch to the correct mode based on the Thumb Exception (TE) bit in the SCTLR. Signed-off-by: Rabin Vincent <rabin@rab.in>
2010-02-06target-arm: refactor cp15.c13 register accessRiku Voipio1-16/+0
Access the cp15.c13 TLS registers directly with TCG ops instead of with a slow helper. If the the cp15 read/write was not TLS register access, fall back to the cp15 helper. This makes accessing __thread variables in linux-user when apps are compiled with -mtp=cp15 possible. legal cp15 register to acces from linux-user are already checked in cp15_user_ok. While at it, make the cp15.c13 Thread ID registers available only on ARMv6K and newer. Signed-off-by: Riku Voipio <riku.voipio@nokia.com>
2009-11-22ARM atomic ops rewritePaul Brook1-84/+0
Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM Cortex-A9 cpu supportPaul Brook1-1/+35
Basic Cortex-A9 support. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-11-19ARM FP16 supportPaul Brook1-0/+16
Implement the ARM VFP half precision floating point extensions. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-10-27target-arm: allow modifying vfp fpexc en bit onlyJuha Riihimäki1-1/+1
All other bits except for the EN in the VFP FPEXC register are defined as subarchitecture specific and real functionality for any of the other bits has not been implemented in QEMU. However, current code allows modifying all bits in the VFP FPEXC register leading to problems when guest code is writing 1's to the subarchitecture specific bits and checking whether the bits stay up to verify the existence of functionality which in fact does not exist in QEMU. This patch has been revised to include the same behavior change in the gdb register write function. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: fix sdiv helperAurelien Jarno1-0/+2
(INT32_MIN / -1) triggers an overflow, and the result depends on the host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a test to output the correct value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23target-arm: use clz32() instead of a for loopAurelien Jarno1-4/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
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